{"id":686978,"url":"https://alion.io/job/lockheed-martin-asic-fpga-design-engineer-sr-e3-3","title":"ASIC & FPGA Design Engineer Sr - E3","company":{"id":37086,"name":"Lockheed Martin","domain":"lockheedmartin.com","url":"https://alion.io/company/lockheedmartin","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"A","score":100,"open_postings":106,"ghost_share":0,"stale_share":0,"repost_share":0.019,"time_to_fill_p50_days":21,"computed_at":"2026-10-01T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Orlando, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":98100,"max":182100,"currency":"USD","period":"year","gross":null,"usd_annual":182100},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"MATLAB","optional":false},{"name":"Simulink","optional":false},{"name":"Synopsys VCS","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Vitis HLS","optional":false},{"name":"Xilinx Vivado","optional":false},{"name":"C++","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-07T20:43:26Z","employer_posted_date":"2026-09-09","last_verified_at":"2026-09-20T14:10:15Z","board_verified":false,"closed_at":null,"days_open":23,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":23},"description":"Standard Job Description\nYou will be the ASIC & FPGA Design Engineer for the ASIC/FPGA department at Lockheed Martin Missiles and Fire Control. Our team creates FPGA-based architectures that power current and next-generation defense systems, delivering highly reliable, high-performance digital solutions for mission-critical applications.\nWhat You Will Be Doing\nAs the FPGA Design Engineer you will lead the digital development of Missile platforms, partnering with algorithm, software, and hardware groups to transform MATLAB/Simulink models into efficient, synthesizable RTL and integrate that RTL onto AMD RFSoC and Versal devices. Your responsibilities will include:\nDefining digital architectures that meet radar/RF-sensor performance, power, and timing requirements.\nConverting algorithmic models from MATLAB/Simulink into high-level synthesis (Vitis HLS) and RTL code (VHDL/Verilog/SystemVerilog).\nWriting, simulating, and verifying RTL and HLS implementations, using self-checking testbenches and functional coverage.\nIntegrating custom and third-party IP blocks, managing clock-domain crossing and timing-closure challenges with Synopsys VCS and Xilinx Vivado tools.\nPerforming place-and-route, timing analysis, and optimization to achieve timing closure on RFSoC/Versal platforms.\nConducting design reviews, delivering clear documentation, and maintaining configuration control in version-control systems.\nCollaborating with algorithm developers, hardware engineers, and software teams to ensure seamless end-to-end system integration.\nLeading mentorship efforts for junior engineers and fostering an inclusive, innovative team culture.\nSupporting system-level validation, debugging, and board-level testing to confirm functional and performance goals.\nWhy Join Us\nDo you want to be part of a company culture that empowers employees to think big, lead with a growth mindset, and make the impossible a reality? We provide the resources and give you the flexibility to enable inspiration and focus. If you have the passion and courage to dream big, work hard, and have fun doing what you love then we want to build a better tomorrow with you.\nWe offer flexible work schedules to comprehensive benefits investing in your future and security. Learn more about Lockheed Martin’s comprehensive benefits package here.\nFurther Information About This Opportunity:\nThis position is in Orlando, FL. Discover more about our Orlando, Florida location.\nMUST BE A U.S. CITIZEN - This position is located at a facility that requires special access. The selected candidate must be able to obtain a secret clearance. An active Secret clearance is required to start.\nBasic Qualifications\nB.S. or M.S. in Electrical/Computer Engineering or a related field\nProficiency in VHDL, Verilog, or SystemVerilog\nExperience with FPGA simulation tools such as Synopsys VCS\nProficiency with timing analysis, clock-domain crossing, and IP integration\nDesired Skills\nExperience converting Simulink/MATLAB models into synthesizable code using Vivado HLS\nExperience with AMD RFSoC and Versal families\nExperience implementing filters, FFTs, beamforming, and other RF-DSP algorithms in hardware\nExperience with the MFC DAR process\nKnowledge of software programming languages such as C, C++, or Python\nPrior work on radar, RF sensor, or high-frequency digital systems\nLeadership experience supporting design reviews, mentoring engineers, or providing cross-functional technical guidance\nExperience with missile applications\nPay Information\nFull-Time Salary Range: $98100.00 - $182100.00\nAt Lockheed Martin, we know mission success starts with taking care of our people. Our Total Rewards program is designed to attract top talent, support your well-being, and help you grow-both professionally and personally.\nThe salary range for this position is as listed on the requisition. Please note that the salary information listed is a general guideline only. Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market(work location) and business considerations when extending an offer.\nBenefits offered: Medical, Dental, Vision, Flexible work arrangements and schedules (e.g., 4x10), 401(k) match, Paid time off, Holidays, Parental Leave, EAP, Flexible Spending Accounts, Education Assistance, Life Insurance, Short-Term Disability, and Long-Term Disability.\nAnnual short-term and/or long-term incentive compensation programs may be offered depending on the position. Payments under these annual programs are not guaranteed and can vary from year to year and are tied to a range of performance metrics.\nFor (Washington state applicants only) Non-represented full-time employees: accrue at least 10 hours per month of Paid Time Off (PTO) to be used for incidental absences and other reasons; receive at least 90 hours for holidays. Represented full time employees accrue 6.67 hours of Vacation per month; accrue up to 52 hours of sick leave annually; receive at least 96 hours for holidays. PTO, Vacation, sick leave, and holiday hours are prorated based on start date during the calendar year.","description_format":"text","description_chars":5187,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":true,"languages":[]},"benefits":["Education assistance","Flexible schedule","Life insurance","Parental leave"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Manufacturing","Satellite Manufacturing","Space Services","Aircraft Manufacturing"],"lifecycle":[{"event":"open","at":"2026-09-11T00:23:25Z"}],"liveness":{"score":29,"band":"fade","label":"Fading","p_open":0.7,"p_active":0.742,"p_room":0.55,"age_days":23,"expected_fill_days":21,"reasons":["conf:255","velocity","win:tail","comp:brand"],"computed_at":"2026-10-01T05:45:00Z"},"pay":{"stated_usd_annual":182100,"is_top_pay":false},"html_url":"https://alion.io/job/lockheed-martin-asic-fpga-design-engineer-sr-e3-3","json_url":"https://alion.io/job/lockheed-martin-asic-fpga-design-engineer-sr-e3-3.json","meta":{"generated_at":"2026-10-01T18:27:01Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":796,"day_limit":5000,"remaining_today":4204,"minute_limit":60,"resets_at":"2026-10-02T00:00:00Z"}}}