{"id":992661,"url":"https://alion.io/job/lockheed-martin-asic-fpga-verification-engineer-sr-stf-e5","title":"ASIC & FPGA Verification Engineer Sr Stf - E5","company":{"id":37086,"name":"Lockheed Martin","domain":"lockheedmartin.com","url":"https://alion.io/company/lockheedmartin","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"A","score":100,"open_postings":106,"ghost_share":0,"stale_share":0,"repost_share":0.019,"time_to_fill_p50_days":21,"computed_at":"2026-10-01T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":185400,"max":344400,"currency":"USD","period":"year","gross":null,"usd_annual":344400},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Linux","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-10T22:58:37Z","employer_posted_date":"2026-09-15","last_verified_at":"2026-10-01T19:47:21Z","board_verified":true,"closed_at":null,"days_open":21,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":21},"description":"Standard Job Description\nPlease join us as an ASIC & FPGA Verification Engineer, where you will be working within the central ASIC & FPGA Engineering division for Lockheed Martin Space. You will have the opportunity to support over 50 different programs and research and development (R&D) efforts. Your work will affect technology across military space, civil space, commercial space, missiles, missile defense platforms, satellite surveillance platforms, deep space exploration, and manned flight missions.\nIN THIS ROLE, YOU WILL:\nWork with low SWaP, radiation hardened, space rated devices.\nDevise a unique verification plan for a given design.\nUse SystemVerilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high-performance computing environment.\nDevelop requirements, test cases, build test benches, generate reports, and document verification results.\nWork with an independent design team to document and resolve bugs found in the design.\nSupport all aspects of ASIC and FPGA development, to include architecture, design, and analysis.\nSupport technical reviews, and be able to present to internal and external stakeholders.\nThe information below reflects the standard job description for this position:\nDevelops, designs, verifies, and documents Application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) development. Determines architecture design, logic design, and system simulation. Assignments include the analysis of all aspects from high-level design to synthesis, place and route, and timing and power utilization. Typically uses specialized equipment to establish operation data, conduct experimental tests, and evaluate results.\nBasic Qualifications\nBachelor of Science or higher from an accredited college in Electrical Engineering or related discipline, or equivalent experience/combined education.\nExperience in the verification of FPGA and/or ASIC devices.\nHDL programming experience with VHDL, Verilog, and/or SystemVerilog.\nWilling and able to obtain and maintain a DoD Secret clearance, thus US Citizenship is required for this position.\nDesired Skills\nMasters or PhD highly preferred.\nExperience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test).\nFPGA/ASIC design experience is a plus.\nExperienced in scripting such as Perl, TCL, Python.\nExperience developing test cases based off given requirements.\nExperience building test benches for FPGA / ASIC designs to provide randomized stimulus.\nExperience identifying and implementing necessary test exclusions.\nExperience generating coverage reports (code and functional)\nExperience or knowledge of MS Project, JIRA.\nExperience leading projects of multiple engineers, managing schedules. prioritizing work and actively communicating with internal or external stakeholders.\nKnowledge of space-grade/qualified FPGAs and ASICs.\nExperience with Earned Value Management System (EVMS).\nExperience mentoring junior engineers.\nProficient in AI prompting as it applies to this position and practice.\nPay Information\nFull-Time Salary Range: $185400.00 - $344400.00\nAt Lockheed Martin, we know mission success starts with taking care of our people. Our Total Rewards program is designed to attract top talent, support your well-being, and help you grow-both professionally and personally.\nThe salary range for this position is as listed on the requisition. Please note that the salary information listed is a general guideline only. Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market(work location) and business considerations when extending an offer.\nBenefits offered: Medical, Dental, Vision, Flexible work arrangements and schedules (e.g., 4x10), 401(k) match, Paid time off, Holidays, Parental Leave, EAP, Flexible Spending Accounts, Education Assistance, Life Insurance, Short-Term Disability, and Long-Term Disability.\nAnnual short-term and/or long-term incentive compensation programs may be offered depending on the position. Payments under these annual programs are not guaranteed and can vary from year to year and are tied to a range of performance metrics.\nFor (Washington state applicants only) Non-represented full-time employees: accrue at least 10 hours per month of Paid Time Off (PTO) to be used for incidental absences and other reasons; receive at least 90 hours for holidays. Represented full time employees accrue 6.67 hours of Vacation per month; accrue up to 52 hours of sick leave annually; receive at least 96 hours for holidays. PTO, Vacation, sick leave, and holiday hours are prorated based on start date during the calendar year.","description_format":"text","description_chars":4777,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":true,"languages":[]},"benefits":["Education assistance","Flexible schedule","Life insurance","Parental leave"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Manufacturing","Military","Defense Manufacturing"],"lifecycle":[{"event":"open","at":"2026-09-17T04:51:00Z"}],"liveness":{"score":39,"band":"fade","label":"Fading","p_open":0.7,"p_active":0.742,"p_room":0.75,"age_days":20,"expected_fill_days":21,"reasons":["conf:255","velocity","win:late","comp:brand"],"computed_at":"2026-10-01T05:45:00Z"},"pay":{"stated_usd_annual":344400,"is_top_pay":true},"html_url":"https://alion.io/job/lockheed-martin-asic-fpga-verification-engineer-sr-stf-e5","json_url":"https://alion.io/job/lockheed-martin-asic-fpga-verification-engineer-sr-stf-e5.json","meta":{"generated_at":"2026-10-02T02:49:22Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":3818,"day_limit":5000,"remaining_today":1182,"minute_limit":60,"resets_at":"2026-10-03T00:00:00Z"}}}