{"id":3760365,"url":"https://alion.io/job/lockheed-martin-senior-asic-fpga-design-engineer-2","title":"Senior ASIC & FPGA Design Engineer","company":{"id":37086,"name":"Lockheed Martin","domain":"lockheedmartin.com","url":"https://alion.io/company/lockheedmartin","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"A","score":96,"open_postings":2381,"ghost_share":0.01,"stale_share":0,"repost_share":0.199,"time_to_fill_p50_days":34,"computed_at":"2026-11-06T05:58:05Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Grand Prairie, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":98100,"max":182100,"currency":"USD","period":"year","gross":null,"usd_annual":182100},"salary_estimate":null,"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"GitLab","optional":false},{"name":"Python","optional":false},{"name":"Synopsys VCS","optional":false},{"name":"SystemC","optional":false},{"name":"SystemVerilog","optional":false},{"name":"TCP/IP","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Vitis","optional":false},{"name":"Vitis HLS","optional":false},{"name":"Xilinx Vivado","optional":false},{"name":"C++","optional":true},{"name":"HDL Coder","optional":true},{"name":"MATLAB","optional":true},{"name":"Simulink","optional":true},{"name":"Synplify Pro","optional":true},{"name":"Tcpdump","optional":true},{"name":"Wireshark","optional":true}],"status":"live","first_seen_at":"2026-10-28T00:39:17Z","employer_posted_date":"2026-11-04","last_verified_at":"2026-11-06T23:25:31Z","board_verified":true,"closed_at":null,"days_open":10,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":10},"description":"Standard Job Description\nLockheed Martin Missiles and Fire Control (MFC) is seeking a Senior ASIC & FPGA Design Engineer to join our Programmable Logic Design team. MFC is a recognized designer, developer, and manufacturer of precision engagement aerospace and defense systems for the U.S. and allied militaries. This role offers an excellent working environment with a mix of cutting-edge digital design, hands-on laboratory testing, and product development. You will work with and learn from industry-leading circuit design professionals in a collaborative, mission-driven environment.\nWhat You Will Be Doing\nThe Senior ASIC & FPGA Design Engineer will serve as a key technical contributor on one or more defense programs, leading the design, verification, and integration of advanced FPGA-based solutions. Responsibilities may include:\nDefining architecture and design specifications for programmable logic components, developing and documenting RTL (VHDL/Verilog/SystemVerilog) that meets performance, power, and reliability requirements\nCreating synthesis, place and route, and timing closure strategies to ensure deterministic operation across target FPGA devices\nGenerating comprehensive test plans, simulation models, and verification environments (UVM, SystemC, Python-based testbenches) to validate functional correctness and timing margins\nLeading hardware-in-the-loop (HIL) testing, board-level debugging, and integration with subsystem-level hardware\nTranslating system-level performance, safety, and reliability requirements into detailed FPGA architectures\nConducting timing analysis, power budgeting, and resource utilization studies to optimize device selection and FPGA utilization\nManaging configuration control (GitLab or equivalent), maintaining version-controlled design repositories, and ensuring traceability of all artifacts\nProducing comprehensive design documentation, including specifications, test plans, verification reports, and release packages compliant with aerospace standards\nCollaborating with cross-functional teams - systems, software, hardware, mechanical, test, manufacturing, and quality - to ensure seamless integration and compliance with program milestones\nProviding technical mentorship to junior engineers and promoting best practices in FPGA development, verification, and configuration management\nThis position offers the opportunity to work alongside experienced ASIC & FPGA design professionals and gain exposure to cutting-edge defense technology.\nCandidates may be subject to a government security investigation and must meet eligibility requirements for access to classified information.\nBasic Qualifications\nBachelor of Science degree in Electrical Engineering or a closely related STEM field from an accredited university; Master’s degree preferred\nMinimum 3 years of professional experience with FPGA design and simulation verification or a related discipline\nProficiency in HDL programming with VHDL, Verilog, and/or SystemVerilog\nExperience with Xilinx/AMD toolsets (Vivado, Vitis, Vitis HLS) and UltraScale design methodology\nExperience with FPGA simulation tools such as Synopsys VCS\nStrong understanding of digital design principles, including timing analysis, clock domain crossing, and signal integrity\nExperience with high-speed interfaces such as AXI, Ethernet, TCP/IP, PCIe, and serial protocols\nPractical laboratory debug experience with high-speed oscilloscopes, spectrum analyzers, and signal generators\nFamiliarity with Synopsys EDA tools\nMust be a US Citizen; must possess a DoD Secret clearance\nDesired Skills\nLM/MFC design experience and missile program experience\nExperience with SystemVerilog, Verilog, C/C++, MATLAB/Simulink; Synopsys Synplify, Synopsys VCS, NCSim, ChipScope tool sets\nExperience with Xilinx/AMD and MicroSemi/Microchip part families, internal FPGA fabric and IP\nExperience implementing NSA algorithms (e.g., AES, counter mode)\nExperience managing configuration control (GitLab preferred)\nExperience with Vivado and Vitis FPGA toolsets\nExperience with UVM and Simulink/HDL Coder integration\nComfortable using digital oscilloscopes, spectrum analyzers, power meters, signal generators, and other test equipment\nExperience with troubleshooting and debugging at board level, including FPGA validation\nExperience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test)\nStrong communication, collaboration, and presentation abilities\nControls and digital loop-closure application knowledge\nNetworking proficiency with Ethernet switches, routers, firewalls, and debugging tools (tcpdump, Wireshark)\nActive DoD Top Secret clearance\nPay Information\nFull-Time Salary Range: $98100.00 - $182100.00\nAt Lockheed Martin, we know mission success starts with taking care of our people. Our Total Rewards program is designed to attract top talent, support your well-being, and help you grow-both professionally and personally.\nThe salary range for this position is as listed on the requisition. Please note that the salary information listed is a general guideline only. Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market(work location) and business considerations when extending an offer.\nBenefits offered: Medical, Dental, Vision, Flexible work arrangements and schedules (e.g., 4x10), 401(k) match, Paid time off, Holidays, Parental Leave, EAP, Flexible Spending Accounts, Education Assistance, Life Insurance, Short-Term Disability, and Long-Term Disability.\nAnnual short-term and/or long-term incentive compensation programs may be offered depending on the position. Payments under these annual programs are not guaranteed and can vary from year to year and are tied to a range of performance metrics.\nFor (Washington state applicants only) Non-represented full-time employees: accrue at least 10 hours per month of Paid Time Off (PTO) to be used for incidental absences and other reasons; receive at least 90 hours for holidays. Represented full time employees accrue 6.67 hours of Vacation per month; accrue up to 52 hours of sick leave annually; receive at least 96 hours for holidays. PTO, Vacation, sick leave, and holiday hours are prorated based on start date during the calendar year.","description_format":"text","description_chars":6363,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":true,"languages":[]},"benefits":["Education assistance","Flexible schedule","Life insurance","Parental leave"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Aerospace Manufacturing","Combat Aircraft","Missiles","Military Satellites"],"lifecycle":[{"event":"open","at":"2026-11-04T18:18:14Z"}],"visa":[{"country":"US","licensed_sponsor":true,"adverts_offering_sponsorship_24m":0,"sanctioned_now":false,"evidence":"H-1B filings in 12 months: 1","filings_12m":1,"filings_prev_12m":1,"green_card_filings_12m":0,"median_offered_wage_usd":182500,"route":null,"cap_exempt":false,"checked_at":"2026-11-06T22:30:08+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":0}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":9,"expected_fill_days":34,"reasons":["conf:0","velocity","win:early","comp:brand"],"computed_at":"2026-11-06T05:58:05Z"},"pay":{"stated_usd_annual":182100,"is_top_pay":false},"html_url":"https://alion.io/job/lockheed-martin-senior-asic-fpga-design-engineer-2","json_url":"https://alion.io/job/lockheed-martin-senior-asic-fpga-design-engineer-2.json","meta":{"generated_at":"2026-11-07T01:44:12Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":4239,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-08T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":37086},"rest":"https://alion.io/mcp/rest/get_company?id=37086"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Flockheed-martin-senior-asic-fpga-design-engineer-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Flockheed-martin-senior-asic-fpga-design-engineer-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Flockheed-martin-senior-asic-fpga-design-engineer-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/lockheed-martin-senior-asic-fpga-design-engineer-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Flockheed-martin-senior-asic-fpga-design-engineer-2"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3760365}},{"tool":"search_jobs","arguments":{"company":"lockheedmartin.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3760365},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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