{"id":694931,"url":"https://alion.io/job/logosspace-senior-fpgaasic-modem-engineer","title":"Senior FPGA/ASIC Modem Engineer","company":{"id":716959,"name":"Logos Space","domain":"logos.space","url":"https://alion.io/company/logos-6","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"C","score":56,"open_postings":19,"ghost_share":0.737,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-31T05:58:55Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Mountain View, United States","San Diego, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":220000,"max":280000,"currency":"USD","period":"year","gross":null,"usd_annual":280000},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cocotb","optional":false},{"name":"Git","optional":false},{"name":"Linux","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Xilinx Vivado","optional":false},{"name":"C++","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-07-20T22:15:53Z","employer_posted_date":"2026-07-20","last_verified_at":"2026-10-31T07:28:44Z","board_verified":true,"closed_at":null,"days_open":102,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":102},"description":"Senior FPGA/ASIC Modem Engineer\nAbout Logos Space\nLogos Space is a Low Earth Orbit (LEO) satellite system purpose-built to serve the connectivity needs of the commercial enterprise users and government users. We will help fill an important gap in the market, providing resilient, high-performance satellite-based connectivity services to enterprise and government customers worldwide. Business customers have contracts with agreed-upon performance standards for their broadband, and Logos will build these capabilities into the system from the beginning. Speed and reliability are the foundation of the system. Logos is designed to extend cloud and data center network connectivity anywhere in the world to fixed, seaborne, and airborne terminals.\nLogos is led by a team of highly experienced engineers with proven track records in the networking and satellite industries.\nPosition Summary\nThe Baseband Modem hardware team at Logos Space is building a high-performance digital modem payload for the Logos LEO satellite system that supports high-throughput, secure, reliable and resilient communications with an emphasis on waveform flexibility using Software Defined Radio (SDR) technology.\nAs a Senior FPGA Modem Engineer, you will design, implement, verify and release FPGA-based modem solutions for end-to-end wireless satellite communications links. You will work closely with the modem systems team on realization of waveform designs using fixed-point FPGA digital hardware and DSP blocks. This role is an exciting opportunity to help build a LEO satellite communications system from the ground up using cutting-edge FPGA technology.\nWe are looking for digital FPGA hardware engineers who can work well in a fast-paced environment, turn sometimes ambiguous requirements into practical hardware implementations, and collaborate closely with adjacent teams.\nResponsibilities\nOwn one or more FPGA-based modem chains through all development phases, from micro-architecture through to lab deployment.\n\nDefine the micro-architecture of high-rate FPGA modem blocks and surrounding digital infrastructure. Implement designs using SystemVerilog or Verilog.\n\nDevelop block-level and end-to-end self-checking hardware verification environments using golden reference models provided by the modem systems team.\n\nDevelop FPGA synthesis and place and route build scripts including timing and placement constraints. Analyze results and implement design changes required to close timing and meet system-level FPGA power and resource requirements.\n\nDefine and implement clean hardware/software interfaces, including registers, configuration, telemetry, fault and status signaling, and test hooks.\n\nConduct code and design reviews and participate in multi-functional reviews.\n\nCollaborate with systems architects, HW engineering design teams and FW/SW design teams for lab bring-up of boards combining FPGA, firmware, RF, and Networking functions.\n\nMentor junior engineers and provide technical leadership on FPGA best practices.\n\nBasic Qualifications\nBachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field.\n\nA minimum of 10+ years experience in design, development and implementation of wireless baseband modems using FPGA devices. Equivalent experience in ASIC modem design will also receive consideration.\n\nProficiency in one or more HDL programming languages such as VHDL, Verilog, or SystemVerilog.\n\nExperience writing verification frameworks using SystemVerilog/UVM, Cocotb or transactional-level modeling.\n\nThorough knowledge of modern FPGA architecture including experience with advanced floorplanning clock-domain crossing (CDC) analysis, false-path isolation, and timing closure techniques . Experience using these techniques with AMD UltraScale+ and Versal FPGA families is highly preferred.\n\nDeep understanding of Digital Front End (DFE) architectures, including digital up/down conversion (DUC/DDC), interpolation/decimation filters, and interfacing with high-speed ADCs and DACs.\n\nExperience with industry-standard bus interfaces such as AXI and AXI-streaming and high-speed interfaces such as DDR4/5, 10/40/100 Gb Ethernet and SERDES interfaces like JESD-204B/C, Aurora and Interlaken.\n\nExperience with FPGA toolchains and workflows such as AMD Vivado, including simulation, synthesis, place-and-route, timing analysis and closure as well as power analysis.\n\nExperience debugging FPGA or digital hardware in the lab using oscilloscopes, logic analyzers, spectrum analyzers, time-interval measurement tools, or similar instrumentation.\n\nExperience working with embedded software design, especially in complex debugging of FPGA on-target SW/HW interaction.\n\nFamiliarity with Linux-based development environments, Git, and automated testing.\n\nStrong written and verbal communication and interpersonal skills. Ability to prioritize work, complete multiple tasks and work under deadlines with minimal supervision.\n\nPreferred Qualifications\nExperience implementing both the MAC and PHY layers of a wireless modem such as 5G OFDMA or Single-Carrier DVB-S2(X) through the entire product life cycle for an FPGA or ASIC target.\n\nExperience with space, defense, or other reliability-critical electronics, including radiation-tolerant design, Triple Modular Redundancy (TMR), and single-event upset (SEU) mitigation techniques.\n\nExperience with embedded firmware or low-level software for device control, board bring-up, telemetry, and calibration workflows.\n\nExperience with board-level digital or mixed-signal hardware design, schematic review, clock-tree or oscillator circuitry and hardware bring-up.\n\nExperience writing tests and automation scripts using C, C++ or Python.\n\nExperience designing HW accelerators tightly coupled with the embedded processor subsystems present in most modern FPGA devices.\n\nExperience with the architecture, toolchains and programming of SIMD vector DSP engines for wireless modem applications.\n\nEven if you don’t meet every qualification, we encourage you to apply. We value strong fundamentals, sound judgment, and growth potential, and we know great candidates do not always match every item on a job description.\nAdditional Information\nLogos Space is an equal opportunity employer and values creativity, curiosity, and diverse perspectives. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, national origin, age, disability, veteran status, marital status, or any other status protected by applicable law. Employment offers are contingent on the candidate’s ability to access export-controlled information in accordance with U.S. law.","description_format":"text","description_chars":6731,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Satellite Manufacturing"],"lifecycle":[{"event":"open","at":"2026-09-11T01:44:19Z"}],"visa":[],"liveness":{"score":8,"band":"cold","label":"Long shot","p_open":1,"p_active":0.274,"p_room":0.28,"age_days":102,"expected_fill_days":28,"reasons":["conf:2","stale_co","ghost","win:tail","crowd:"],"computed_at":"2026-10-31T05:58:55Z"},"pay":{"stated_usd_annual":280000,"is_top_pay":true},"html_url":"https://alion.io/job/logosspace-senior-fpgaasic-modem-engineer","json_url":"https://alion.io/job/logosspace-senior-fpgaasic-modem-engineer.json","meta":{"generated_at":"2026-10-31T11:03:04Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":16979,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-01T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":716959},"rest":"https://alion.io/mcp/rest/get_company?id=716959"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Flogosspace-senior-fpgaasic-modem-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Flogosspace-senior-fpgaasic-modem-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Flogosspace-senior-fpgaasic-modem-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/logosspace-senior-fpgaasic-modem-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Flogosspace-senior-fpgaasic-modem-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":694931}},{"tool":"search_jobs","arguments":{"company":"logos.space","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":694931},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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