Qual Engineer

Responsible for qualification and validation of server hardware platforms including CPUs memory storage networking and peripherals

Execute system level test plans covering functionality performance stress and reliability

Analyze failures perform root cause debugging and work with design and firmware teams on issue resolution

Develop and automate test scriptstools for hardware validation and regression testing

Ensure compliance with quality standards interoperability requirements and customer specifications

Document test results track defects and support release readiness of server platforms

Working experience using Kusto or similar scripting languages accessing large

Working experience using SAW machines or similar tools for node health investigations

Patent or track record of engineering excellency

Experience with Liquid Cooling Systems in Data Centers

1 years of system level server debugging with an understanding of power system and network environments

Leadership skills and ability to collaborate with diverse teams and drive a call to action

Expert of root cause analysis and corrective action methods to identify contributing factors of production defects

Ability to analyze large data sets extract key insights and effectively present and communicate the results

Proficient communication skills

This role often requires a mix of handson lab work bench software development bench software hardware integration bench setup running characterization tests and close collaboration with crossfunctional teams

The ideal candidate is a selfstarter highly motivated engineer with excellent technical interpersonal skills used to working independently or as a key member of a fastmoving design team

Responsibilities

The primary responsibility of this position entails executing the silicon validation and characterization of cutting edge high performance highspeed low power CMOS D2D and SERDES silicon interface following industry best practices

You will be responsible for all or parts of the following areas

Bring up validate and characterize highspeed D2D and SERDES in new and existing silicon chips

Bench software and hardware integration bench setup

Develop test methods to evaluate performance and calculate operating margins of highspeed serial interfaces across various conditions

Collaborate with design teams to improve testability and define test infrastructure logic

Write software routines eg Python,C++ to bring up and validate D2D and SERDES IPs and integrate drivers with software teams

Analyze test results and document findings to provide insights and recommendations