1,591,724open jobs
95,632companies
242,839added this week
Browse all
Location
Hybrid
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 13, 2026. First seen by Alion on Mar 23, 2026.

Overview
Company
Impact
Profile match
Formal verification sign-off service for digital IP&SoCs. LUBIS EDA helps teams reduce risk and reach predictable, high-confidence sign-off on critical designs.
Backed by Helmholtz

Your mission

You own a defined formal deliverable end-to-end (days to a few weeks). You work independently in known contexts, drive proof closure, and hand over sign-off artifacts that customers trust.
  • Own a block/area: clarify requirements, co-define the verification strategy (scope, risks, approach), execute, and close.
  • Produce maintainable SVA and a clean formal environment (constraints/assumptions with good hygiene).
  • Debug efficiently, partner with designers on fixes, and prevent regressions.
  • Keep stakeholders aligned with crisp updates and decision-ready evidence.

Your profile

  • Proven experience delivering formal results on non-trivial RTL (e.g., caches, pipelined processors, DMAs, NoCs).
  • Strong SVA skills and hands-on formal tool experience (e.g.: Jasper, VCF, Questa Formal/Onespin).
  • Reliable end-to-end ownership in a defined scope.

What success looks like in your first ~90 days

  • You nail our onboarding bootcamp and earn the team’s trust: you apply the LUBIS way of working and consistently ship clean, reviewable outputs.
  • You engage confidently in scoping and planning with the team: you clarify open questions early, surface risks, and help translate scope into a concrete plan.
  • You own a deliverable end-to-end in a defined area and ship it without a “rescuer”.

Where this leads

The natural next step is our Senior Formal Verification Engineer role - leading customer engagements, owning formal architecture decisions, mentoring Associates and Professionals, and shaping how LUBIS approaches new verification problems. We make that path concrete: review cycles, customer-lead rotations, and clear competency milestones.

Free account
Stop reading job ads. Get the ones that fit.
One free account turns this page into a shortlist built around your stack, your level and your pay.
Match on every job. Stack, seniority, pay and location, scored against your profile.
1,591,724 open roles. Read straight off company career pages, refreshed every day.
Unlimited applications. Every one you send is tracked in one place, on-site or on a company board.
3 tailored CVs a month. Rewritten for the exact job you are applying to. Included free.
Create a free account Continue with Google
Free forever. No card. Under a minute.

Your match

How well do you fit this role?
Two answers are enough for a real match. No account needed.
Check my fit
Answers stay in this browser until you create an account.

Recommended for you based on this role

Hardware
Similar stack
Same company
In your city
≈ $16k – $42k per year (Estimated) • In office • Bachelor's Degree • Novosibirsk
C++
C++
CMake
DevOps
CI/CD
Git
Linux
Apply
≈ $41k – $76k per year (Estimated) • In office • Full-Time • Poitiers
Apply
$168k – $245k per year • Equity • Hybrid • Full-Time • 7+ years exp • Bachelor's Degree • San Jose • Austin
Python
SystemVerilog
Perl
Chips/EDA
UVM
Synopsys Verdi
Apply
$168k – $245k per year • Equity • Hybrid • Full-Time • 7+ years exp • Bachelor's Degree • San Jose
Python
Verilog
Perl
Chips/EDA
Tessent
Synopsys Verdi
Synopsys TestMAX
Apply
$187k – $268k per year • Equity • Hybrid • Full-Time • 8+ years exp • Bachelor's Degree • San Jose
Python
SystemVerilog
Perl
Chips/EDA
UVM
Synopsys Verdi
Apply
Chip Lead 4 days ago
$161k – $298k per year • Equity • In office • Full-Time • 12+ years exp • Master's Degree • Austin
Python
Verilog
SystemVerilog
Perl
Chips/EDA
Formal Verification
Apply
$213k – $288k per year • Equity • In office • Full-Time • 6+ years exp • Bachelor's Degree • Austin
Python
PowerShell
Perl
AI/ML
AWS Trainium
Machine Learning
DevOps
AWS
Chips/EDA
Formal Verification
Apply
≈ $22k – $50k per year (Estimated) • In office • Full-Time • 7+ years exp • Master's Degree • Taipei • Zhubei
Python
Perl
Chips/EDA
Formal Verification
Apply
$180k – $220k per year • Hybrid • Full-Time • 10+ years exp • Bachelor's Degree • Austin
Python
SystemVerilog
DevOps
Linux
Chips/EDA
UVM
Formal Verification
Apply
≈ $98k – $183k per year (Estimated) • In office • 10+ years exp • Bachelor's Degree • Jacksonville
Verilog
VHDL
Chips/EDA
Formal Verification
Apply
Hybrid • Full-Time
SystemVerilog
Chips/EDA
Cadence JasperGold
Formal Verification
OneSpin
Synopsys VC Formal
Apply
Hybrid • Full-Time
Apply
See all jobs
This is one of many
1,591,724 more open roles from verified company boards, updated every day.