{"id":1170268,"url":"https://alion.io/job/lumilens-ic-layout-engineer-optical-engine-silicon","title":"IC Layout Engineer – Optical Engine Silicon","company":{"id":678172,"name":"Lumilens","domain":"lumilens.com","url":"https://alion.io/company/lumilens","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"A","score":95,"open_postings":54,"ghost_share":0,"stale_share":0.019,"repost_share":0,"time_to_fill_p50_days":122,"computed_at":"2026-09-30T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Singapore"],"countries":["SG"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":39000,"max_usd":107000,"period":"year","method":"role_country_seniority_unknown","sample_n":73},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Python","optional":false},{"name":"Synopsys StarRC","optional":false},{"name":"KLayout","optional":true}],"status":"live","first_seen_at":"2026-09-24T06:26:31Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-09-29T21:19:54Z","board_verified":true,"closed_at":null,"days_open":6,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":6},"description":"The role\nLumilens builds optical interconnect for AI data centers: silicon photonics, mixed-signal ICs, electrical-optical interposers, and the systems around them. Our silicon ships in production AI clusters today, and volume is climbing fast.\nYou will own layout for our electronic ICs (EICs) and photonic ICs (PICs). These are high-speed analog blocks where the layout is the design: a parasitic you did not anticipate, a return path you did not control, or a current density you did not check will cost the part its margin.\nYou will also support photonic IC (PIC) layout as our schedule demands, and own the integration of electronic and photonic dies as they come together.\nSingapore puts you close to the assembly and test supply chain we depend on, working alongside a senior layout engineer and partnering with design teams across the US, India, and Singapore.\nResponsibilities\nOwn layout for assigned analog and mixed-signal blocks: device placement, matching and symmetry, shielding, guard rings, and routing, from floorplan through to clean sign-off.\n\nExecute parasitic-aware layout - build to the constraints given by designers, run extraction, and take the results back to them when the layout says something the schematic did not expect.\n\nRoute high-speed signal paths with attention to impedance, coupling, and return paths, and lay out passive and electromagnetic structures under senior direction.\n\nRun and close DRC, LVS, antenna, and density checks on your blocks, and support electromigration and IR drop analysis.\n\nSupport top-level assembly and chip finishing activities through tape out.\n\nSupport PIC layout as the need arises, including waveguide and curvilinear structures.\n\nLay out photonic components and waveguide routing - bends, tapers, couplers, grating and edge couplers, and modulator and photodetector electrodes - from designer-provided geometry, honoring minimum bend radius, waveguide spacing, and phase- and length-matching constraints.\n\nRun photonics-specific verification: curvilinear DRC against the photonics PDK, waveguide connectivity and port checks, LVS on custom photonic cells, and clean GDS stream-out for tape out.\n\nBuild the scripts and reusable structures that make the layout team faster.\n\nQualifications\nDiploma, BS, or MS in Electrical or Electronics Engineering, or equivalent hands-on layout experience.\n\n1-3 years in custom analog, RF, or mixed-signal IC layout, including at least one tapeout you contributed to through to silicon.\n\nSolid working experience with Cadence Virtuoso, including Layout XL and constraint-driven flows.\n\nParasitic awareness in practice - you understand why a matched pair is drawn the way it is, and which nets on your block deserve the extra care.\n\nFundamentals in electromigration and IR drop: current density limits, power routing, and the checks that catch problems.\n\nFundamentals in electromagnetics for on-chip structures - coupling, shielding, and why high-speed routing is constrained the way it is.\n\nPhysical verification experience: Calibre or PVS DRC/LVS, and parasitic extraction with QRC, StarRC, or equivalent.\n\nSome scripting for layout automation - SKILL, Python, or both.\n\nWillingness to overlap with US and India hours during tape out crunch.\n\nPreferred Qualifications\nSiGe BiCMOS layout experience, and the passive and isolation practices those processes demand.\n\nAdvanced FinFET CMOS layout at 7nm and below - multi-patterning and coloring, fin and poly grid constraints, and the DRC complexity that comes with them.\n\nPhotonic IC layout exposure: waveguide routing, curvilinear geometry, and photonics PDK design rules.\n\nExperience with parametric photonic cells (PCells) in Virtuoso SKILL or Python-based photonic layout tools (gdsfactory, KLayout, IPKISS), and with curvilinear-to-grid snapping and fracture rules.\n\nFamiliarity with silicon photonics building blocks and their layout sensitivities: Mach-Zehnder and ring modulators, Ge photodetectors, thermal phase shifters, and fiber coupling structures.\n\nExposure to 2.5D and 3D integration, interposers, or micro-bump and copper pillar arrays.\n\nLayout on optical front ends specifically - TIA, modulator driver, or high-speed serial link blocks.\n\nWhy this role\nOptical I/O for AI is being defined right now, and in this silicon the layout is where the performance is actually won. The team is small, so the blocks are yours: you will take them from floorplan to tapeout, see them come back as working parts, and grow into top-level and methodology ownership as we scale. You will also get a working foot in photonics, which very few layout engineers have.","description_format":"text","description_chars":4617,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Servers & Data Center Hardware","Optical Communications","Optics & Photonic Components"],"lifecycle":[{"event":"open","at":"2026-09-24T06:59:52Z"}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":5,"expected_fill_days":122,"reasons":["conf:8","velocity","win:early","comp:brand"],"computed_at":"2026-09-30T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/lumilens-ic-layout-engineer-optical-engine-silicon","json_url":"https://alion.io/job/lumilens-ic-layout-engineer-optical-engine-silicon.json","meta":{"generated_at":"2026-09-30T06:51:33Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4930,"day_limit":5000,"remaining_today":70,"minute_limit":60,"resets_at":"2026-10-01T00:00:00Z"}}}