{"id":621903,"url":"https://alion.io/job/lumilens-icrtl-design-engineer","title":"IC/RTL Design Engineer","company":{"id":678172,"name":"Lumilens","domain":"lumilens.com","url":"https://alion.io/company/lumilens","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"A","score":93,"open_postings":56,"ghost_share":0,"stale_share":0.071,"repost_share":0,"time_to_fill_p50_days":118,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":102000,"max_usd":199000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":568},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-07-06T20:26:23Z","employer_posted_date":"2026-07-06","last_verified_at":"2026-10-17T08:37:50Z","board_verified":true,"closed_at":null,"days_open":102,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":102},"description":"IC/RTL Design Engineer/ Front-End Engineer\nAbout the role. You design and implement the digital front-end RTL at the heart of the chip - including the high-speed datapath that moves data between UCIe and the optical front end. Guided by the interface specs and coding standards, you take blocks from micro-architecture through clean, timing-aware RTL and block-level verification. It's a hands-on role with room to grow your scope as the team and the chip mature.\nWhat you'll do\nDevelop block-level micro-architecture for your assigned blocks, and contribute to interface and register definitions.\n\nDesign and implement front-end RTL blocks in SystemVerilog - datapath elements, the UCIe streaming/RDI adapter, elastic FIFOs, and supporting logic.\n\nIntegrate IP and support parameterization for configurability.\n\nWrite clean, lint-clean, CDC/RDC-clean RTL that follows the coding and quality standards.\n\nWrite block-level testbenches, sanity checks, and assertions (SVA) for your own blocks before handoff to DV.\n\nPower- and timing-aware design - managing block activity, clock-gating, pipelining, and retiming; partner with the backend team on physical closure for your blocks.\n\nBring-up and debug across simulation and emulation / FPGA prototyping; support DV and silicon bring-up, including DFT/debug hooks in your blocks.\n\nCollaborate with the architecture, modelling, DV, DFT, and backend teams as your blocks move through the flow.\n\nRequired\nBS or MS in Electrical/Computer Engineering (or equivalent experience).\n\n3+ years of digital RTL design in SystemVerilog, with blocks taken from micro-architecture through to verification handoff.\n\nSolid digital design fundamentals: pipelining, FSMs, FIFOs, clock-domain crossing, and streaming/bus interfaces (e.g., AXI).\n\nLint and CDC/RDC discipline and clean-RTL practices.\n\nPower- and timing-aware design practices; comfort with synthesis and timing closure, working with the backend team.\n\nStrong debug skills in simulation; scripting in Python, Perl, or TCL.\n\nPreferred\nHigh-speed datapath, SerDes-adjacent, or interface design exposure (UCIe, PCIe/CXL, or similar).\n\nFEC/coding datapath familiarity (e.g., Reed-Solomon) and gray-code mapping.\n\nAssertion-based verification (SVA) and familiarity with UVM block-level testbenches; emulation / FPGA prototyping experience.\n\nExposure to scale-up / scale-out interconnects or network switch / NIC / memory-controller datapaths.\n\nLow-power / UPF and DFT (scan) concepts.\n\nOptical transceiver, CPO, or linear-drive optics background; advanced-node (N5/N3/N2) design experience.","description_format":"text","description_chars":2575,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Servers & Data Center Hardware","Optical Communications","Optics & Photonic Components"],"lifecycle":[{"event":"open","at":"2026-09-10T18:47:58Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"Filed H-1B visas in the last two years","filings_12m":0,"filings_prev_12m":1,"green_card_filings_12m":0,"median_offered_wage_usd":null,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":0}],"liveness":{"score":46,"band":"ok","label":"Likely open","p_open":1,"p_active":0.761,"p_room":0.6,"age_days":102,"expected_fill_days":118,"reasons":["conf:0","velocity","win:late","crowd:brand"],"computed_at":"2026-10-17T05:46:00Z"},"pay":null,"html_url":"https://alion.io/job/lumilens-icrtl-design-engineer","json_url":"https://alion.io/job/lumilens-icrtl-design-engineer.json","meta":{"generated_at":"2026-10-17T09:16:27Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":12185,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-18T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":678172},"rest":"https://alion.io/mcp/rest/get_company?id=678172"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Flumilens-icrtl-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Flumilens-icrtl-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Flumilens-icrtl-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/lumilens-icrtl-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Flumilens-icrtl-design-engineer"}]}