{"id":1170267,"url":"https://alion.io/job/lumilens-seniorstaffprincipal-ic-layout-engineer-optical-engine-silicon","title":"Senior/Staff/Principal IC Layout Engineer – Optical Engine Silicon","company":{"id":678172,"name":"Lumilens","domain":"lumilens.com","url":"https://alion.io/company/lumilens","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"A","score":89,"open_postings":149,"ghost_share":0.094,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":118,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Singapore"],"countries":["SG"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":65000,"max_usd":147000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Python","optional":false},{"name":"Synopsys StarRC","optional":false},{"name":"KLayout","optional":true}],"status":"live","first_seen_at":"2026-09-24T06:30:00Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-10-30T15:28:37Z","board_verified":true,"closed_at":null,"days_open":36,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":34},"description":"The role\nLumilens builds optical interconnect for AI data centers: silicon photonics, mixed-signal ICs, electrical-optical interposers, and the systems around them. Our silicon ships in production AI clusters today, and volume is climbing fast.\nYou will own layout for our electronic ICs (EICs) and photonic ICs (PICs). These are high-speed analog blocks where the layout is the design: a parasitic you did not anticipate, a return path you did not control, or a current density you did not check will cost the part its margin.\nYou will also support photonic IC (PIC) layout as our schedule demands, and own the integration of electronic and photonic dies as they come together.\nSingapore puts you close to the assembly and test supply chain we depend on, partnering with design teams across the US, India, and Singapore. You will be the senior layout voice on the ground here.\nResponsibilities\nBlock and top-level layout\nOwn floorplan and layout for high-speed analog and mixed-signal blocks: TIAs, drivers, SerDes front ends, PLL and clocking, references and bias.\n\nExecute device-level matching and symmetry - common-centroid, dummies, shielding, guard rings, substrate isolation - to the level these circuits actually require.\n\nRoute high-speed signal paths with control over impedance, coupling, and return paths. Lay out passive and electromagnetic structures (inductors, transformers, transmission lines) and work with designers through EM simulation.\n\nOwn chip finishing: pad ring, bump and pillar maps, seal ring, density fill, and top-level assembly through tape out.\n\nPhysical closure\nDrive parasitic-aware layout: iterate with designers on extraction results and close the loop between what the schematic assumed and what the layout delivers.\n\nOwn electromigration and IR drop closure - current density, power grid construction, and the analysis that proves it holds at temperature and lifetime.\n\nTake blocks through DRC, LVS, antenna, DFM, and ESD and latch-up checks to sign-off.\n\nPhotonics and integration\nSupport PIC layout as the need arises: waveguide and curvilinear structures, and the design rules that come with a photonics platform.\n\nOwn layout of photonic blocks: waveguide routing under bend-radius, spacing, and length-matching constraints; modulator (MZM, ring) and photodetector electrode layout co-optimized with the RF drive path; and grating and edge coupler placement against fiber-attach and packaging constraints.\n\nBuild and maintain the photonic PCell library and PDK integration in Virtuoso - curvilinear geometry generation, SKILL and Python automation, grid snapping and stream-out, and DRC/LVS methodology for custom photonic cells.\n\nOwn the EIC-PIC integration - micro-bump and pillar alignment, interposer interfaces, and the co-layout decisions that make the electrical path work across two dies.\n\nMethodology and team\nSet layout standards here: reusable structures, PDK and tech file evaluation, automation, documentation, and review practice.\n\nMentor junior layout engineers as the Singapore team grows, and represent layout in design reviews with real authority.\n\nQualifications\nDiploma, BS, or MS in Electrical or Electronics Engineering, or equivalent hands-on layout experience.\n\n8+ years in custom analog, RF, or high-speed mixed-signal IC layout, including multiple tape outs you saw through to silicon.\n\nExpert-level Cadence Virtuoso, including Layout XL and constraint-driven flows.\n\nDeep parasitic awareness - you can look at a schematic and a spec and know which nets will decide whether the block works.\n\nWorking command of electromigration and IR drop fundamentals: current density limits, power grid design, and the checks that sign them off.\n\nElectromagnetics fundamentals for on-chip structures - inductors, transformers, transmission lines, coupling, and shielding.\n\nPhysical verification fluency: Calibre or PVS DRC/LVS, and parasitic extraction with QRC, StarRC, or equivalent.\n\nWillingness to overlap with US and India hours during tapeout crunch.\n\nPreferred Qualifications\nSiGe BiCMOS layout experience, and the passive and isolation practices those processes demand.\n\nAdvanced FinFET CMOS layout at 7nm and below - multi-patterning and coloring, fin and poly grid constraints, and the DRC complexity that comes with them.\n\nPhotonic IC layout exposure: waveguide routing, curvilinear geometry, and photonics PDK design rules.\n\nHands-on silicon photonics layout on a foundry platform (Si and SiN waveguides), including PCell development in Virtuoso SKILL or Python-based photonic layout tools (gdsfactory, KLayout, IPKISS).\n\nUnderstanding of how layout drives photonic performance - propagation loss, phase error, optical and thermal crosstalk.\n\n2.5D and 3D integration, interposers, micro-bump and copper pillar arrays, and co-packaged optics assemblies.\n\nLayout for optical front ends specifically - TIA, modulator driver, or high-speed serial link blocks.\n\nExperience standing up layout methodology for a product line in its first generation, where nothing existed yet.\n\nScripting for layout automation - SKILL, Python, or both.\n\nWhy this role\nOptical I/O for AI is being defined right now, and in this silicon the layout is where the performance is actually won - these are blocks where a few femtofarads and a poorly planned return path decide whether the link closes. You will have real authority over physical design on parts going into production at scale, short lines to the designers whose circuits you are building, and a founding hand in how our Singapore silicon team works.","description_format":"text","description_chars":5550,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Servers & Data Center Hardware","Optical Communications","Optics & Photonic Components"],"lifecycle":[{"event":"open","at":"2026-09-24T06:59:52Z"}],"visa":[],"liveness":{"score":72,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.899,"p_room":0.8,"age_days":35,"expected_fill_days":118,"reasons":["conf:3","velocity","win:early","crowd:brand,attention"],"computed_at":"2026-10-30T05:48:23Z"},"pay":null,"html_url":"https://alion.io/job/lumilens-seniorstaffprincipal-ic-layout-engineer-optical-engine-silicon","json_url":"https://alion.io/job/lumilens-seniorstaffprincipal-ic-layout-engineer-optical-engine-silicon.json","meta":{"generated_at":"2026-10-30T19:04:02Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":8389,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-31T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":678172},"rest":"https://alion.io/mcp/rest/get_company?id=678172"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Flumilens-seniorstaffprincipal-ic-layout-engineer-optical-engine-silicon"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Flumilens-seniorstaffprincipal-ic-layout-engineer-optical-engine-silicon"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Flumilens-seniorstaffprincipal-ic-layout-engineer-optical-engine-silicon"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/lumilens-seniorstaffprincipal-ic-layout-engineer-optical-engine-silicon\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Flumilens-seniorstaffprincipal-ic-layout-engineer-optical-engine-silicon"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":1170267}},{"tool":"search_jobs","arguments":{"company":"lumilens.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":1170267},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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