{"id":1280282,"url":"https://alion.io/job/macrohire-asic-frontend-design-engineer","title":"ASIC Frontend Design Engineer","company":{"id":3800331,"name":"MacroHire","domain":"macrohire.in","url":"https://alion.io/company/macrohire","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Kolkata, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":29000,"max_usd":60000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":375},"experience_years_min":14,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Synopsys Design Compiler","optional":false},{"name":"Synopsys SpyGlass","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-08-19T11:29:26Z","employer_posted_date":null,"last_verified_at":"2026-08-19T11:29:26Z","board_verified":false,"closed_at":null,"days_open":42,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":42},"description":"ASIC Frontend Design Engineer:\n\nWork Location: Kolkata (3 days WFO)\n\nExperience: 1) Engineer (5-12 years & IC role), 2) Manager (14-20 years)\n\nMode of Interview: 2 Rounds Virtual followed by last F2F at Bangalore or Kolkata office.\n\nOpportunity Snapshot:\n\nWe are looking for a highly skilled ASIC Frontend Design Engineer to join our high-performance VLSI team. You will be responsible for designing and delivering next-generation, high-speed ASICs for complex networking and compute systems, while collaborating with global Architecture, Design, Verification, and Physical Design teams. We foster a culture of innovation, ownership, collaboration, and continuous learning, offering excellent opportunities for technical growth and leadership.\n\nKey Responsibilities:\n\n- Design and develop high-performance ASICs and SoC blocks for next-generation products.\n\n- Define microarchitecture, perform RTL design, and optimize for performance, power, and area (PPA).\n\n- Develop high-quality RTL using Verilog/SystemVerilog.\n\n- Collaborate with Verification teams on test planning, functional coverage, debug, and verification closure.\n\n- Work with Physical Design teams on timing constraints, timing analysis, and timing closure.\n\n- Participate in design reviews, root-cause analysis, and silicon bring-up activities.\n\n- Drive cross-functional collaboration with Architecture, Verification, Firmware, Physical Design, and Program Management teams.\n\nRequired Skills:\n\n- Strong RTL coding expertise in Verilog/SystemVerilog.\n\n- Good understanding of SoC architecture, microarchitecture, digital logic, and ASIC design.\n\n- Hands-on experience with SystemVerilog, UVM, SVA, coverage-driven verification, and RTL concepts.\n\n- Knowledge of high-speed protocols such as PCIe, Ethernet, AXI, NoC, DDR/HBM, CXL, UCIe, or cache coherency protocols.\n\n- Experience with high-performance memory subsystems, clock-domain crossing (CDC), and high-speed serial interfaces.\n\n- Familiarity with Synopsys Design Compiler, Formality/LEC, SpyGlass, and other EDA tools is preferred.\n\n- Strong debugging, analytical, and problem-solving skills with excellent written and verbal communication.\n\nPreferred Qualifications:\n\n- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, Microelectronics, VLSI, or a related discipline.\n\n- Experience in networking ASICs, storage, AI/ML accelerators, or high-performance SoCs is highly desirable.\nSkills\nVLSI, ASIC, RTL Design, Verilog, SoC, System Verilog, Synopsys","description_format":"text","description_chars":2476,"description_truncated":false,"requirements":{"experience_years_min":14,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Continuous learning"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Professional Services"],"lifecycle":[{"event":"open","at":"2026-09-26T02:00:24Z"}],"liveness":{"score":20,"band":"cold","label":"Long shot","p_open":0.6,"p_active":0.609,"p_room":0.55,"age_days":41,"expected_fill_days":30,"reasons":["seen:41","win:tail"],"computed_at":"2026-09-30T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/macrohire-asic-frontend-design-engineer","json_url":"https://alion.io/job/macrohire-asic-frontend-design-engineer.json","meta":{"generated_at":"2026-10-01T03:06:23Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":2587,"day_limit":5000,"remaining_today":2413,"minute_limit":60,"resets_at":"2026-10-02T00:00:00Z"}}}