Staff Engineer, Design Verification

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Central IP team provides leading-edge SerDes PHY solutions.

As a member of a digital design development team, you will be designing, developing, and maintaining various hard-macro PHY IPs.

What You Can Expect

Develop verification plans for complex designs. Perform functional verification of RTL designs for One-Time Programmable (OTP) and Post-Quantum Cryptography (PQC) modules, including maintaining regression test suites. Develop comprehensive test plans and implement verification tests using SystemVerilog and UVM methodologies. Create and maintain UVM Register Abstraction Layer (RAL) models utilizing scripting languages such as Python and Perl. Support development and maintenance of UVM-based memory and register environments for ASIC verification. Utilize industry-standard tools such as Verdi for waveform debugging and GVim for code editing and maintenance. Analyze simulation results, debug failures, and collaborate with design teams to resolve issues. Document verification processes and results to ensure compliance with design specifications. Wage $137,000.00 - $167,000.00 per year.

What We're Looking For

Master’s or foreign equivalent degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

Must have work/internship experience or completed graduate coursework/research in each of the following:

• SystemVerilog.
• RTL Coding.
• UVM (Universal Verification Methodology).
• Design specification analysis and test plan development.
• Version control tools and methodology.
• RTL simulators (VCS, Questa).
• Writing testbench for functional simulation and verification.
• Scripting languages: Python and Perl.
• Design specification analysis and test plan development.
• SOC/CPU sub-system design.
• Industry standard Verilog simulators such as Questa or Cadence.
• C/C++ programming.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.