{"id":2106565,"url":"https://alion.io/job/marvell-technology-staff-engineer-design-verification","title":"Staff Engineer, Design Verification","company":{"id":269,"name":"Marvell Technology","domain":"marvell.com","url":"https://alion.io/company/marvell-technology","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":95,"open_postings":47,"ghost_share":0,"stale_share":0.191,"repost_share":0.021,"time_to_fill_p50_days":54,"computed_at":"2026-10-12T06:55:09Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":137000,"max":167000,"currency":"USD","period":"year","gross":null,"usd_annual":167000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"C++","optional":false},{"name":"ChatGPT","optional":false},{"name":"Copilot","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"closed","first_seen_at":"2026-10-08T20:35:46Z","employer_posted_date":"2026-10-08","last_verified_at":"2026-10-11T10:34:54Z","board_verified":false,"closed_at":"2026-10-11T10:34:54Z","days_open":2,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":2},"description":"About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.\nYour Team, Your Impact\nCentral Engineering AMS-IP development. Deliver high-speed SerDes IPs.Central IP team provides leading-edge SerDes PHY solutions.\nAs a member of a digital design development team, you will be designing, developing, and maintaining various hard-macro PHY IPs.\nWhat You Can Expect\nDevelop verification plans for complex designs. Perform functional verification of RTL designs for One-Time Programmable (OTP) and Post-Quantum Cryptography (PQC) modules, including maintaining regression test suites. Develop comprehensive test plans and implement verification tests using SystemVerilog and UVM methodologies. Create and maintain UVM Register Abstraction Layer (RAL) models utilizing scripting languages such as Python and Perl. Support development and maintenance of UVM-based memory and register environments for ASIC verification. Utilize industry-standard tools such as Verdi for waveform debugging and GVim for code editing and maintenance. Analyze simulation results, debug failures, and collaborate with design teams to resolve issues. Document verification processes and results to ensure compliance with design specifications. Wage $137,000.00 - $167,000.00 per year.\nWhat We're Looking For\nMaster’s or foreign equivalent degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\nMust have work/internship experience or completed graduate coursework/research in each of the following:\nSystemVerilog.\nRTL Coding.\nUVM (Universal Verification Methodology).\nDesign specification analysis and test plan development.\nVersion control tools and methodology.\nRTL simulators (VCS, Questa).\nWriting testbench for functional simulation and verification.\nScripting languages: Python and Perl.\nDesign specification analysis and test plan development.\nSOC/CPU sub-system design.\nIndustry standard Verilog simulators such as Questa or Cadence.\nC/C++ programming.\n\nThis role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\nInterview Integrity\nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n#LI-TT1","description_format":"text","description_chars":4552,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[{"name":"United States","iso":"US"}],"relocation_offered":false,"industries":["Data Centers & Colocation","Threat Intelligence","Network Equipment","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-08T20:35:46Z"},{"event":"close","at":"2026-10-11T10:34:54Z"}],"visa":[],"liveness":null,"pay":{"stated_usd_annual":167000,"is_top_pay":false},"html_url":"https://alion.io/job/marvell-technology-staff-engineer-design-verification","json_url":"https://alion.io/job/marvell-technology-staff-engineer-design-verification.json","meta":{"generated_at":"2026-10-12T09:20:57Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":14149,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-13T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":269},"rest":"https://alion.io/mcp/rest/get_company?id=269"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fmarvell-technology-staff-engineer-design-verification"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fmarvell-technology-staff-engineer-design-verification"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fmarvell-technology-staff-engineer-design-verification"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/marvell-technology-staff-engineer-design-verification\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fmarvell-technology-staff-engineer-design-verification"}]}