{"id":1469508,"url":"https://alion.io/job/maxlinear-principal-engineer-memory-architect","title":"Principal Engineer Memory Architect","company":{"id":64219,"name":"Maxlinear","domain":"maxlinear.com","url":"https://alion.io/company/maxlinear","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"iCIMS","truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Carlsbad, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":135000,"max":198000,"currency":"USD","period":"year","gross":null,"usd_annual":198000},"salary_estimate":null,"experience_years_min":9,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Cadence Virtuoso","optional":true},{"name":"Python","optional":true},{"name":"Synopsys HSPICE","optional":true},{"name":"Wi-Fi","optional":true}],"status":"live","first_seen_at":"2026-09-29T15:42:29Z","employer_posted_date":"2026-09-29","last_verified_at":"2026-09-30T00:34:58Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Responsibilities\nMaxLinear is seeking a Principal Engineer Memory Architect to join our team. In this role, you will focus on the following:\nDesign, define, evaluate, and optimize memory intellectual property across advanced technology nodes\nLeverage your memory architecture expertise, circuit-level understanding, and system-level awareness to deliver high-performance, power-efficient, area-optimized, and reliable memory solutions for SoC integration\nWork closely with IP and SoC teams to provide technical direction for memory IP roadmaps, architecture selection, compiler evaluation, and trade-off decisions involving PPA and robustness\nOwn the design and optimization of memory architectures, based on SRAMs, ROMs, and register files, using memory compilers or custom designs\nDeliver competitive memory IP solutions and enabling seamless integration into SoCs\nCollaborate with cross-functional engineering teams and external IP vendors, and developing scalable QA methodologies, automation flows, and verification frameworks for consistent memory IP evaluation\nQualifications\nDeep understanding of embedded SRAM and register-file architectures, including bit-cell fundamentals, array layout considerations, and PPA trade-offs\nStrong knowledge of low-power techniques, read/write assist techniques, design stability and robustness, design margining and power integrity considerations\nExperience analyzing memory behavior across PVT corners and evaluating timing, reliability, signal integrity, and SoC-level trade-offs\nStrong understanding of memory compiler flows and verification methodologies, with the ability to assess both compiled and custom memory solutions\nExcellent communication skills and ability to collaborate effectively across multidisciplinary teams and influence technical decisions at both strategic and hands-on levels\nPreferred QualificationsProficiency with EDA and analysis tools HSPICE, Spectre, Python, and related memory verification or modeling environments\nFamiliarity with SoC design flows and interactions among memory IP, standard cells, I/O libraries, clocking, system buses, and interface protocols\nFamiliarity with ROMs, flash memories, OTPs is a plus\nUnderstanding of advanced-node scaling, PVT variation impacts, memory behavior across corners, and silicon validation practices\nFamiliarity with transistor-level circuit design and analysis, and experience using IC design or simulation tools such as HSPICE, Spectre, or Cadence Virtuoso, is a plus\nExperience with QA methodologies, validation frameworks, technical roadmaps\n\nBS in Electrical Engineering or related + 9 years of experience, or MS + 7 years of experience, or Ph.D. + 4 years of experience \nCompensation and Benefits\nMaxLinear has a Total Compensation philosophy which includes base salary and annual discretionary bonus eligibility and many positions also include stock-based compensation.\nMaxLinear's good faith estimate starting base salary range is: $135,000 to $198,000 Annually\nWe offer competitive benefits designed to support employee health, welfare, and retirement and some highlights are: health care benefits, 401k savings plan, Employee Stock Purchase Plan (ESPP), and paid time off.\nThe actual starting base salary will be determined by the match to certain role-related criteria such as educational degree(s) or equivalent, relevant work experience, skillset needed for the role, and geographic location; this is not an all-inclusive list as some roles may require unique skills or experience.\nQualified applicants will receive consideration for employment without regard to, and will not be discriminated against based on race, sex, religion, national origin, sexual orientation, gender identity, disability, or protected veteran status.\nCompany Overview\nMaxLinear is a global, NASDAQ-traded company (MXL) where the entrepreneurial spirit is alive and well. We are a fabless system-on-chip product company, striving to improve the world’s communication networks for everyone through our highly integrated radio-frequency (RF), analog, digital, and mixed-signal semiconductor solutions for access and connectivity, wired and wireless infrastructure, and industrial and multi-market applications.\nWe hire the best people in the industry and engage them in some of the most exciting opportunities that connect the world we live in today. Our growth has come from innovative, bold approaches to solving some of the world’s most challenging communication technology problems in the most efficient and effective manner.\nMaxLinear began by developing the world’s first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn’t achieve the extremely high-performance requirements using CMOS, but we proved them wrong and achieved enduring global market leadership with our designs. Since then, we’ve developed a full line of products that drive 4G and 5G infrastructure; enable data center, metro and long-haul optical interconnects; bring 10Gbit to the home; power the IoT revolution; and enable robust and reliable communication in harsh industrial environments. Over the years, we’ve expanded through organic growth and through several acquisitions that have perfectly complemented our existing portfolio and enabled us to deliver complete end-to-end solutions in our target markets. One such example was the acquisition of Intel’s Home Gateway Platform Division that added Wi-Fi, Ethernet, and Broadband Gateway Processor SoC technology to our connected home portfolio creating a complete and scalable platform of connectivity and access solutions to fully address our customers’ needs.\nOur headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Valencia, Spain; Bangalore, India; Munich, Germany; Israel; and Singapore.\nWe have approximately 1,200 employees, a substantial majority of whom have engineering degrees and include masters and Ph.D. graduates from many of the premiere universities around the world. Our employees thrive on innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. Together, we form a high-energy business team that is focused on building the best and most innovative products on the market.","description_format":"text","description_chars":6283,"description_truncated":false,"requirements":{"experience_years_min":9,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["401k plan"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless Hardware","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-09-29T15:42:29Z"}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":1,"expected_fill_days":31,"reasons":["conf:29","velocity","win:early"],"computed_at":"2026-10-01T05:45:00Z"},"pay":{"stated_usd_annual":198000,"is_top_pay":true},"html_url":"https://alion.io/job/maxlinear-principal-engineer-memory-architect","json_url":"https://alion.io/job/maxlinear-principal-engineer-memory-architect.json","meta":{"generated_at":"2026-10-01T18:11:56Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":430,"day_limit":5000,"remaining_today":4570,"minute_limit":60,"resets_at":"2026-10-02T00:00:00Z"}}}