{"id":4048530,"url":"https://alion.io/job/maxlinear-senior-principal-digital-soc-design-engineer","title":"Senior Principal Digital SoC Design Engineer","company":{"id":64219,"name":"Maxlinear","domain":"maxlinear.com","url":"https://alion.io/company/maxlinear","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"iCIMS","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Wi-Fi","optional":false}],"status":"live","first_seen_at":"2026-11-11T00:57:26Z","employer_posted_date":"2026-11-11","last_verified_at":"2026-11-11T00:57:26Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Responsibilities\nMaxLinear is seeking a Senior Principal Digital SoC Design Engineer to join our Analog Mixed Signal (AMS) group in San Jose, CA. The AMS team develops a broad portfolio of integrated solutions spanning high speed and embedded connectivity interfaces (bridges, serial transceivers, isolators) and power management, supporting data center, industrial, and embedded platforms. In this role, you will lead digital architecture and RTL for a roadmap of products ranging from USB-based connectivity bridges to PCIe-to-USB host bridge devices, to complex embedded-processor SoCs for data center platform management, and will focus on the following:\nLead digital architecture and RTL for USB device-side connectivity bridges, including multi-port serial (UART), I²C/SPI/GPIO bridging, endpoint/FIFO architecture, flow control, and OTP-based configurability and customization\nArchitect and integrate PCIe-to-USB host bridge solutions, including PCIe endpoint and USB host controller (xHCI) integration, DMA engines, buffer management, interrupt and power-state handling, and driver-visible register architecture\nDefine and lead digital architecture for complex embedded-processor SoCs for data center platform management, including multi-core Arm subsystems, memory controllers, high speed host interfaces, sideband management buses, and peripheral-rich I/O\nDrive platform security and management features, including secure boot, hardware root of trust, cryptographic checksum generator and checker, and host-to-management communication paths\nMaximize reuse of existing digital IP across product generations, and drive make, reuse, or license decisions for USB, PCIe, and other interface controllers and PHYs\nDefine on-chip interconnect, clock/reset, low-power, and DFT architecture, and own RTL quality through lint, CDC/RDC, synthesis, timing constraints, and implementation closure\nSet verification strategy with the DV team, including compliance and interoperability readiness, emulation/FPGA prototyping, and firmware/driver co-verification\nPartner closely with analog/mixed-signal, PHY, firmware, software, package, test, and applications teams from concept through silicon bring up, compliance, qualification, and production\nMentor senior engineers, lead design reviews, and act as the digital technical authority across connectivity and SoC roadmap\nQualifications\nDeep hands-on expertise in SystemVerilog/Verilog RTL design, SoC micro-architecture, and complex top-level integration\nStrong working knowledge of USB 2.0/3.x device and host architectures (including xHCI) and PCIe endpoint architecture, with experience integrating licensed controller and PHY IP\nExperience with serial and peripheral interfaces (UART, I²C/I3C, SPI, GPIO) and bridge-type data paths, FIFOs, and DMA\nExperience integrating embedded Arm processor subsystems, DDR/memory controllers, bus fabrics (AMBA AXI/AHB/APB), and security IP; familiarity with data center server management concepts (e.g., eSPI, I3C, MCTP, hardware root of trust) is a strong plus\nStrong understanding of clock/reset, CDC/RDC, low-power design, timing constraints, synthesis, DFT, and physical design trade-offs\nTrack record delivering multiple SoCs from architecture through tapeout, silicon bring up, compliance certification, and high-volume production\nExperience working with external design partners and IP vendors, and ability to lead technically across multiple disciplines and global teams\nBS in Electrical Engineering or related + 15 years of experience, or MS + 12 years of experience, or Ph.D. + 9 years of experience\nCompensation and Benefits\nMaxLinear has a Total Compensation philosophy which includes base salary and annual discretionary bonus eligibility and many positions also include stock-based compensation.\nMaxLinear's good faith estimate starting base salary range is: $200,000 to $250,000 Annually\nWe offer competitive benefits designed to support employee health, welfare, and retirement and some highlights are: health care benefits, 401k savings plan, Employee Stock Purchase Plan (ESPP), and paid time off.\nThe actual starting base salary will be determined by the match to certain role-related criteria such as educational degree(s) or equivalent, relevant work experience, skillset needed for the role, and geographic location; this is not an all-inclusive list as some roles may require unique skills or experience.\nQualified applicants will receive consideration for employment without regard to, and will not be discriminated against based on race, sex, religion, national origin, sexual orientation, gender identity, disability, or protected veteran status.\nCompany Overview\nMaxLinear is a global, NASDAQ-traded company (MXL) where the entrepreneurial spirit is alive and well. We are a fabless system-on-chip product company, striving to improve the world’s communication networks for everyone through our highly integrated radio-frequency (RF), analog, digital, and mixed-signal semiconductor solutions for access and connectivity, wired and wireless infrastructure, and industrial and multi-market applications.\nWe hire the best people in the industry and engage them in some of the most exciting opportunities that connect the world we live in today. Our growth has come from innovative, bold approaches to solving some of the world’s most challenging communication technology problems in the most efficient and effective manner.\nMaxLinear began by developing the world’s first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn’t achieve the extremely high-performance requirements using CMOS, but we proved them wrong and achieved enduring global market leadership with our designs. Since then, we’ve developed a full line of products that drive 4G and 5G infrastructure; enable data center, metro and long-haul optical interconnects; bring 10Gbit to the home; power the IoT revolution; and enable robust and reliable communication in harsh industrial environments. Over the years, we’ve expanded through organic growth and through several acquisitions that have perfectly complemented our existing portfolio and enabled us to deliver complete end-to-end solutions in our target markets. One such example was the acquisition of Intel’s Home Gateway Platform Division that added Wi-Fi, Ethernet, and Broadband Gateway Processor SoC technology to our connected home portfolio creating a complete and scalable platform of connectivity and access solutions to fully address our customers’ needs.\nOur headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Valencia, Spain; Bangalore, India; Munich, Germany; Israel; and Singapore.\nWe have approximately 1,200 employees, a substantial majority of whom have engineering degrees and include masters and Ph.D. graduates from many of the premiere universities around the world. Our employees thrive on innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. Together, we form a high-energy business team that is focused on building the best and most innovative products on the market.","description_format":"text","description_chars":7182,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["401k plan"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","Processors, MCUs & AI Chips","RF & Wireless Hardware","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-11-11T00:57:26Z"}],"visa":[{"country":"US","licensed_sponsor":true,"adverts_offering_sponsorship_24m":0,"sanctioned_now":false,"evidence":"H-1B filings in 12 months: 17 · green card filings: 10","filings_12m":17,"filings_prev_12m":19,"green_card_filings_12m":10,"median_offered_wage_usd":146389,"route":null,"cap_exempt":false,"checked_at":"2026-11-10T11:34:35+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":10}],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":46,"reasons":["conf:1","win:early"],"computed_at":"2026-11-11T02:33:47Z"},"pay":null,"html_url":"https://alion.io/job/maxlinear-senior-principal-digital-soc-design-engineer","json_url":"https://alion.io/job/maxlinear-senior-principal-digital-soc-design-engineer.json","meta":{"generated_at":"2026-11-11T02:33:47Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":766,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-12T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":64219},"rest":"https://alion.io/mcp/rest/get_company?id=64219"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fmaxlinear-senior-principal-digital-soc-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fmaxlinear-senior-principal-digital-soc-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fmaxlinear-senior-principal-digital-soc-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/maxlinear-senior-principal-digital-soc-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fmaxlinear-senior-principal-digital-soc-design-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":4048530}},{"tool":"search_jobs","arguments":{"company":"maxlinear.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":4048530},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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