{"id":1185639,"url":"https://alion.io/job/mediatek-analog-mixed-signal-design-verification-engineer","title":"Analog Mixed-Signal Design Verification Engineer","company":{"id":62191,"name":"MediaTek","domain":"mediatek.com","url":"https://alion.io/company/mediatek","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"A","score":85,"open_postings":370,"ghost_share":0.165,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":112,"computed_at":"2026-10-28T05:59:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":18000,"max_usd":41000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":843},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"C++","optional":true},{"name":"Linux","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"SystemC","optional":true},{"name":"Unix","optional":true}],"status":"live","first_seen_at":"2025-07-17T16:00:00Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-10-28T21:09:01Z","board_verified":true,"closed_at":null,"days_open":468,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":467},"description":"Job FunctionWork on functional verification of analog and mixed-signal IPs, including SERDES, sensors, and beyond. The candidate will collaborate with IP design teams and other verification teams, utilizing and enhancing both established and emerging digital verification methodologies and processes. Responsibilities span the full verification lifecycle-from understanding specifications and developing test plans, to achieving coverage closure and supporting post-silicon debug-to ensure high-quality and efficient pre-silicon verification, ultimately delivering robust silicon products.\nSkills/Experience\nQuick learner with strong critical thinking and creative problem-solving skills.\nSolid knowledge in ASIC verification flow, digital design, and UVM-based design verification methodologies.\nProficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).\nProficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.\nKnowledge on Design Verification development process, from specification to test plan, to configurable test bench, drivers, and checkers development, to test suite building to meet functional and code coverage goals,\n3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal IPs or SERDES IPs, such as USB, UFS, PCIe, DDR-PHY, MIPI etc.\nPower-aware simulations and gate level simulations is a plus.\nScripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., Perforce, ClearCase, etc.) is a plus.\nKnowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus.\nFamiliar with programming languages: C, C++, and/or SystemC is a plus.","description_format":"text","description_chars":1852,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless Hardware","AI Chips & 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