{"id":1185320,"url":"https://alion.io/job/mediatek-data-center-datacenter-compute-soc-architect","title":"<Data Center> Datacenter Compute SoC Architect","company":{"id":62191,"name":"MediaTek","domain":"mediatek.com","url":"https://alion.io/company/mediatek","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"A","score":87,"open_postings":360,"ghost_share":0.142,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":121,"computed_at":"2026-10-16T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hsinchu, Taiwan"],"countries":["TW"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":30000,"max_usd":62000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":557},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"SystemC","optional":false}],"status":"live","first_seen_at":"2026-08-03T16:00:00Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-10-17T02:02:36Z","board_verified":true,"closed_at":null,"days_open":74,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":73},"description":"Role SummaryWe are seeking a highly experienced and visionary Datacenter Compute SoC Architect to lead the definition, design, and optimization of our next-generation high-performance computing SoCs. In this critical role, you will be responsible for defining the system-on-chip architecture for scalable datacenter processors, balancing Power, Performance, and Area (PPA) constraints while meeting aggressive cloud-scale workloads.\nYou will work cross-functionally with CPU/Compute core architects, IP designers, performance modeling teams, and software/firmware engineers to deliver world-class silicon that powers the future of cloud computing and AI infrastructure.\nKey Responsibilities\nSoC Architecture Definition: Lead the architectural definition of next-generation datacenter Compute SoCs, including core/instance counts, cache hierarchies, coherent interconnects, and memory subsystems.\nIP Selection & Integration: Define requirements and drive decisions for third-party and internal IPs (e.g., PCIe Gen 5/6, CXL, DDR5/HBM controllers, Network-on-Chip/NoC, and security enclaves).\nPPA Optimization: Conduct rigorous Power, Performance, and Area (PPA) trade-off analysis to ensure the SoC meets strict datacenter efficiency and performance-per-watt targets.\nAdvanced Packaging Strategy: Collaborate with packaging teams on multi-die/chiplet-based architectures, die-to-die (D2D) interconnect protocols (e.g., UCIe), and advanced thermal solutions.\nHW/SW Co-Design: Partner closely with firmware, OS, and cloud infrastructure software teams to ensure the hardware architecture optimally supports modern hypervisors, cloud-native workloads, and virtualization technologies.\nPerformance Modeling: Work with the performance modeling team to define use cases, guide the creation of C++/SystemC architectural models, and analyze simulation data to identify bottlenecks.\nTechnical Leadership: Write detailed architecture specifications and serve as the technical lead during the RTL implementation, verification, and silicon bring-up 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