{"id":1185318,"url":"https://alion.io/job/mediatek-data-center-datacenter-compute-soc-performance-modeling-architect","title":"<Data Center> Datacenter Compute SoC Performance Modeling Architect","company":{"id":62191,"name":"MediaTek","domain":"mediatek.com","url":"https://alion.io/company/mediatek","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"A","score":86,"open_postings":360,"ghost_share":0.15,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":118,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hsinchu, Taiwan"],"countries":["TW"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":29000,"max_usd":61000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":557},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Bottleneck","optional":false},{"name":"C++","optional":false},{"name":"Python","optional":false},{"name":"SystemC","optional":false},{"name":"Cython","optional":true}],"status":"live","first_seen_at":"2026-08-03T16:00:00Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-10-17T10:02:07Z","board_verified":true,"closed_at":null,"days_open":74,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":74},"description":"Role SummaryWe are looking for a highly skilled Datacenter Compute SoC Performance Modeling Engineer. In this role, you will be at the forefront of defining our next-generation cloud and datacenter processors. You will develop and maintain high-speed, cycle-accurate, and transaction-level architectural simulators to evaluate design trade-offs, identify performance bottlenecks, and project system performance across a wide range of datacenter workloads.\nYou will collaborate closely with CPU/Compute core architects, SoC architects, IP architects, workload characterization teams, and RTL designers to ensure our silicon delivers industry-leading performance-per-watt and scales efficiently to meet the demands of modern hyper-scale infrastructure.\nKey Responsibilities\nSimulator Development: Design, develop, and maintain cycle-accurate and transaction-level performance models (C++/SystemC) for multi-core datacenter SoCs, including CPU cores, memory subsystems, interconnects (NoC), and high-speed I/O (PCIe/CXL).\nWorkload Analysis & Profiling: Analyze and characterize cloud-native workloads, microservices, databases, and AI/ML data processing pipelines to drive architectural requirements.\nPerformance Exploration: Conduct what-if analyses and architectural design sweeps to optimize cache sizes, memory bandwidth, latency, interconnect topologies, and core counts.\nBottleneck Identification: Identify micro-architectural and system-level performance bottlenecks and propose innovative hardware or software solutions.\nRTL & Silicon Correlation: Work with RTL verification and post-silicon validation teams to correlate the performance model against RTL simulations, emulators, and actual silicon, ensuring model accuracy.\nTooling & Infrastructure: Build and enhance tracing tools, data visualization dashboards, and automated performance regression pipelines using Python and data analysis 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