{"id":1185223,"url":"https://alion.io/job/mediatek-data-centerdesign-engineer-die-to-die-interface","title":"<Data center>Design Engineer - Die-to-Die Interface","company":{"id":62191,"name":"MediaTek","domain":"mediatek.com","url":"https://alion.io/company/mediatek","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"C","score":64,"open_postings":342,"ghost_share":0.599,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-09-25T05:45:01Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hsinchu, Taiwan"],"countries":["TW"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":37000,"max_usd":99000,"period":"year","method":null,"sample_n":6553},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false}],"status":"live","first_seen_at":"2026-09-22T16:00:00Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-09-25T02:30:43Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":2},"description":"Join our next-generation HPC SoC team to build cutting-edge Chiplet interconnect solutions. Whether you are an experienced architect or a recent graduate with strong fundamentals, this role offers a clear path to becoming a specialist in UCIe, D2D, and Advanced Packaging technologies. We value potential and provide the mentorship needed to grow into the role.1. Develop Die-to-die and UCIe digital IP for HPC SOC.\nDesign and implement robust digital IP blocks that enable high-bandwidth, low-latency communication across chiplets in complex HPC systems.\n2. Integration of D2D controller and PHY to timing closure and DFT.\nDrive the integration flow between controllers and PHY layers, ensuring timing closure sign-off and implementing design-for-test strategies for manufacturing quality.\n3. Define interface specifications, creating comprehensive verification plans, and support integration and physical implementation.\nOwn the interface definition lifecycle, develop rigorous verification plans, and collaborate on physical implementation.\n4. Work closely with multiple teams such as mixed mode designers and Firmware engineers.\nPartner across disciplines to align on system-level goals, debug complex integration issues, and ensure seamless firmware-hardware co-design.\n#LI-LYNN","description_format":"text","description_chars":1283,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless Hardware","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-24T14:44:02Z"}],"liveness":{"score":60,"band":"ok","label":"Likely open","p_open":1,"p_active":0.602,"p_room":1,"age_days":2,"expected_fill_days":22,"reasons":["conf:3","stale_co","win:early","comp:brand"],"computed_at":"2026-09-25T05:45:01Z"},"pay":null,"html_url":"https://alion.io/job/mediatek-data-centerdesign-engineer-die-to-die-interface","json_url":"https://alion.io/job/mediatek-data-centerdesign-engineer-die-to-die-interface.json","meta":{"generated_at":"2026-09-26T03:13:44Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":3428,"day_limit":5000,"remaining_today":1572,"minute_limit":60,"resets_at":"2026-09-27T00:00:00Z"}}}