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Salary
≈ $59k – $106k per year (Estimated)
Location
In office (Austin)
Seniority
Junior
Visa
H-1B filings in 12 months: 104 · green card filings: 55

Confirmed on the employer's own hiring board on Oct 24, 2026. First seen by Alion on Oct 19, 2026. MediaTek scores A on the Alion truth index.

Overview
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Impact
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MediaTek Inc. is a global fabless semiconductor company specializing in system-on-chip (SoC) architectures and digital multimedia processing technologies. The enterprise designs and markets integrated circuits for smartphones, smart home devices, IoT hardware, wireless connectivity solutions, automotive electronics, and custom AI chips for edge and cloud applications. Headquartered in Hsinchu, Taiwan, the organization operates an international network of research, development, and sales offices serving original equipment manufacturers (OEMs) and technology brands worldwide.
MediaTek is a global fabless semiconductor industry leader, providing solutions from the edge to the cloud and powering over 2 billion connected devices every year. Established in 1997, our leading-edge technologies keep the world connected and enhance everyday life. At the forefront of innovation, MediaTek drives advancements in transformative technologies such as AI, 5G/6G, Wi-Fi 8, and Embedded IoT. Our high-performance, power-efficient solutions form the foundation for a smarter, more connected world - enabling everything from smartphones, smart homes, and AI PCs to high-performance computing, automotive, embedded IoT systems, and AI data centers. As a trusted partner to the world's leading brands, we are committed to ensuring access to world-class technology for everyone. Our dedication to accelerating AI underscores our mission to enrich the future of humanity.

We are looking for a Design-for-Test (DFT) Engineer to support high-performance (>4 GHz) CPU subsystems using the latest DFT methodologies and techniques. In this role, you will help define and implement DFT architectures to meet test coverage goals, generate and simulate test patterns, and support post-silicon validation activities.

Key Responsibilities

Contribute to DFT architecture definition and implementation for high-performance CPU subsystems.

Generate test patterns and simulate them at gate level to validate correctness and coverage.

Support post-silicon validation by generating, analyzing, and debugging failing patterns on silicon.

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