{"id":2585676,"url":"https://alion.io/job/mediatek-design-verification-technical-manager-high-speed-io-pcie-usb","title":"Design Verification Technical Manager (High-Speed IO: PCIe & USB)","company":{"id":62191,"name":"MediaTek","domain":"mediatek.com","url":"https://alion.io/company/mediatek","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"A","score":85,"open_postings":368,"ghost_share":0.166,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":112,"computed_at":"2026-10-26T05:57:25Z"}},"role":"Leadership","role_family":"Leadership","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hsinchu, Taiwan"],"countries":["TW"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":23000,"max_usd":68000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":2356},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"LLM","optional":false},{"name":"Prompt Engineering","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-14T16:00:00Z","employer_posted_date":"2026-10-15","last_verified_at":"2026-10-26T08:41:16Z","board_verified":true,"closed_at":null,"days_open":11,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":11},"description":"Role OverviewWe are seeking two Senior Design Verification Engineers to architect and execute comprehensive verification strategies for our next-generation high-performance SoCs. In this role, you will take technical ownership of IP-level and subsystem-level verification for mission-critical high-speed serial protocols, specifically PCIe and USB.\nBeyond standard UVM and constrained-random methodologies, you will be a catalyst for modernizing our verification flow-integrating AI/LLM-assisted workflows to accelerate test writing, assertion generation, log triage, and coverage closure.\nKey Responsibilities\n1.Testbench Architecture & Test Planning\na. Define, author, and review detailed Verification Plans (vPlans) from architectural and micro-architectural specifications through tape-out sign-off.\nb. Architect, build, and maintain modular, scalable, and reusable UVM-based testbenches from scratch, including custom drivers, monitors, scoreboards, predictors, and reference models.\nc. Drive constrained-random test generation, SystemVerilog Assertions (SVA), and functional coverage metrics to achieve 100% coverage sign-off.\n2.High-Speed Subsystem & Protocol Verification\na. Lead IP- and subsystem-level verification for PCIe (Gen 4/5/6) and USB (USB 3.2 / USB4 / Type-C) controllers and PHY interfaces (PIPE/UTMI).\nb. Verify complex protocol dynamics, including:\ni. Link Training and Status State Machine (LTSSM) transitions and recovery loops.\nii. Low-power states (ASPM L0s, L1, L1.1/L1.2, USB U1/U2/U3) and power management handshakes.\niii. Equalization, credit flow control, split transactions, packet ordering, and error injection/recovery flows.\niv. Integrate and debug industry-standard Verification IPs (VIPs) from leading vendors (Synopsys, Cadence, Avery/Siemens).\n3.Automation, Tooling & Infrastructure\na. Build scripts for regression health monitoring, automated failure extraction, seed sweeping, and automated coverage report merging.\nb. Collaborate closely with Design, Emulation, Firmware, and Post-Silicon Validation teams to debug complex system-level failures.\n4.AI & LLM-Augmented Verification Workflows\na. Actively deploy and refine LLM-assisted techniques to accelerate the DV lifecycle:\nb. Leverage AI tools to generate boilerplate UVM components, corner-case test vectors, and SVA properties from design specs.\nc. Implement automated triage agents using LLMs to ingest simulation log files, pinpoint root-cause failure signatures, and summarize crash states.\nd. Optimize prompt engineering and programmatic interfaces (APIs, CLI scripts) to build reproducible team-wide verification copilots.","description_format":"text","description_chars":2625,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless Hardware","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-15T03:57:40Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":11,"expected_fill_days":112,"reasons":["conf:1","velocity","win:early","comp:brand"],"computed_at":"2026-10-26T05:57:25Z"},"pay":null,"html_url":"https://alion.io/job/mediatek-design-verification-technical-manager-high-speed-io-pcie-usb","json_url":"https://alion.io/job/mediatek-design-verification-technical-manager-high-speed-io-pcie-usb.json","meta":{"generated_at":"2026-10-26T10:44:33Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":14506,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-27T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":62191},"rest":"https://alion.io/mcp/rest/get_company?id=62191"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fmediatek-design-verification-technical-manager-high-speed-io-pcie-usb"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fmediatek-design-verification-technical-manager-high-speed-io-pcie-usb"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fmediatek-design-verification-technical-manager-high-speed-io-pcie-usb"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/mediatek-design-verification-technical-manager-high-speed-io-pcie-usb\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fmediatek-design-verification-technical-manager-high-speed-io-pcie-usb"}]}