{"id":1185613,"url":"https://alion.io/job/mediatek-formal-verification","title":"Formal Verification","company":{"id":62191,"name":"MediaTek","domain":"mediatek.com","url":"https://alion.io/company/mediatek","size_band":null,"is_staffing_agency":false,"is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":34000,"max_usd":74000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":978},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemC","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Synopsys VC Formal","optional":true},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2025-11-18T16:00:00Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-09-25T02:30:43Z","board_verified":true,"closed_at":null,"days_open":310,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":310},"description":"Job FunctionFunctional Formal Verification Engineer - Lead\nWe are seeking an experienced Functional Formal Verification Engineer to join our team and lead formal verification efforts for complex digital designs. As a Lead Formal Verification Engineer, you will play a critical role in ensuring the quality and reliability of our digital designs.\nQualifications:\nBachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field.\n5+ years of experience in formal verification of complex IP/SubSystem/SoCs, with a strong understanding of digital logic design and verification techniques.\nExpertise in formal verification tools and property specification languages (e.g., SVA, PSL), as well as proficiency in HDLs such as System Verilog, Verilog or VHDL.\nExperience with industry-standard EDA formal tools.\nExperience with scripting languages (e.g., Python, Tcl, Perl) and programming languages such as C/C++/SystemC.\nExcellent problem-solving and analytical skills, with the ability to debug complex issues and optimize verification performance.\nStrong communication and interpersonal abilities, with experience working in a team environment and collaborating with cross-functional teams.\nProven track record in technical leadership and mentoring, with experience guiding junior engineers and contributing to the development of formal verification methodologies.\nResponsibilities\nLead complete formal verification for single or multiple design blocks and IPs, including developing and implementing formal verification strategies and test plans.\nCreate comprehensive formal verification test plans and specifications to ensure thorough coverage of design functionality.\nProve design properties, identify bugs, and collaborate with design teams to improve micro-architectures and ensure design correctness.\nCraft innovative solutions for verifying complex design architectures, including developing re-usable and optimized formal models and verification code bases.\nMentor junior team members and provide technical leadership in formal verification methodologies, including training and guidance on industry-standard tools and techniques.\nCollaborate with cross-functional teams, including design and verification, to ensure seamless integration of formal verification into the overall verification flow.\nPreferred Skills:\nExperience with CPU, GPU, or other complex digital architectures, including knowledge of industry-standard protocols (e.g., AXI, CHI, PCIe).\nFamiliarity with UVM methodology and/or other simulation-based verification methodologies.\nExperience with advanced FV performance optimization techniques, such as abstraction methods, property decomposition, and other state-space reduction techniques.\nExpertise in Jasper or VC Formal products is highly desirable.\nJob Locations\nIndia: Bangalore","description_format":"text","description_chars":2850,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Semiconductors","Wireless"],"lifecycle":[{"event":"open","at":"2026-09-24T14:44:02Z"}],"liveness":{"score":6,"band":"cold","label":"Long shot","p_open":1,"p_active":0.198,"p_room":0.28,"age_days":310,"expected_fill_days":24,"reasons":["conf:0","win:tail","crowd:brand"],"computed_at":"2026-09-25T02:42:00Z"},"pay":null,"html_url":"https://alion.io/job/mediatek-formal-verification","json_url":"https://alion.io/job/mediatek-formal-verification.json","meta":{"generated_at":"2026-09-25T02:42:00Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":2887,"day_limit":5000,"remaining_today":2113,"minute_limit":60,"resets_at":"2026-09-26T00:00:00Z"}}}