{"id":1185347,"url":"https://alion.io/job/mediatek-fpga-lead-engineer","title":"FPGA Lead Engineer","company":{"id":62191,"name":"MediaTek","domain":"mediatek.com","url":"https://alion.io/company/mediatek","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"A","score":85,"open_postings":368,"ghost_share":0.166,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":112,"computed_at":"2026-10-26T05:57:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hsinchu, Taiwan"],"countries":["TW"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":29000,"max_usd":66000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-07-14T16:00:00Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-10-26T12:58:55Z","board_verified":true,"closed_at":null,"days_open":103,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":103},"description":"• Lead FPGA development activities across functional prototyping, emulation, performance evaluation, and database generation flows.Work closely with architecture, design, verification, software, firmware, and performance teams to understand system requirements and define FPGA implementation strategy.\nDrive FPGA functional flow, including RTL integration, FPGA partitioning, synthesis, place-and-route, timing constraints, timing closure, bitstream generation, bring-up, and debug.\nDrive FPGA performance flow to support in-house performance evaluation, workload execution, data collection, profiling, and performance database generation.\nDesign, implement, integrate, and optimize FPGA logic using Verilog/SystemVerilog/VHDL.\nDevelop and maintain FPGA prototypes and emulation platforms for system validation, software enablement, firmware development, and hardware/software debug.\nSupport performance analysis by enabling representative workloads, collecting runtime metrics, identifying bottlenecks, and collaborating with architecture/design teams on improvement opportunities.\nDefine and improve FPGA methodology, automation, build flows, regression infrastructure, and debug processes for both functional and performance use cases.\nSupport and integrate interfaces such as PCIe, DDR, AXI, Ethernet, SPI, I2C, UART, and other standard protocols.\nProvide technical leadership, mentor engineers, coordinate cross-functional execution, and drive issue resolution across multi-site teams.\n#LI-LL1","description_format":"text","description_chars":1498,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless Hardware","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-24T14:44:02Z"}],"visa":[],"liveness":{"score":49,"band":"ok","label":"Likely open","p_open":1,"p_active":0.814,"p_room":0.6,"age_days":103,"expected_fill_days":112,"reasons":["conf:1","velocity","win:late","crowd:brand"],"computed_at":"2026-10-26T05:57:25Z"},"pay":null,"html_url":"https://alion.io/job/mediatek-fpga-lead-engineer","json_url":"https://alion.io/job/mediatek-fpga-lead-engineer.json","meta":{"generated_at":"2026-10-26T13:05:25Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":18151,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-27T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":62191},"rest":"https://alion.io/mcp/rest/get_company?id=62191"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fmediatek-fpga-lead-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fmediatek-fpga-lead-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fmediatek-fpga-lead-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/mediatek-fpga-lead-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fmediatek-fpga-lead-engineer"}]}