{"id":1185622,"url":"https://alion.io/job/mediatek-ip-dft-engineer","title":"IP DFT Engineer","company":{"id":62191,"name":"MediaTek","domain":"mediatek.com","url":"https://alion.io/company/mediatek","size_band":"1001-5000","is_staffing_agency":false,"is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":71000,"max_usd":177000,"period":"year","method":"role_country_seniority_unknown","sample_n":4852},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2025-10-10T16:00:00Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-09-25T02:30:43Z","board_verified":true,"closed_at":null,"days_open":349,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":349},"description":"We are seeking a skilled and motivated Mixed-Signal IP DFT Engineer to join our design team. In this role, you will be responsible for developing and implementing Design for Test (DFT) strategies for mixed-signal IP blocks, ensuring high test coverage and manufacturability. You will work closely with analog, digital, and verification engineers to deliver robust and testable mixed-signal IP solutions.Key Responsibilities:\nDevelop and implement DFT architectures and methodologies for mixed-signal IP blocks, including scan insertion and test point insertion for digital portions, and test enablement for analog circuits.\nCollaborate with analog and digital design teams to ensure DFT requirements are incorporated during IP development.\nPerform DFT verification, including ATPG (Automatic Test Pattern Generation), fault simulation, and coverage analysis for digital logic.\nWork with Integration DFT teams to integrate IP-level DFT features into larger systems.\nDocument DFT design, verification, and test procedures for mixed-signal IPs.\nStay current with industry trends and best practices in mixed-signal DFT and testability.","description_format":"text","description_chars":1131,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Semiconductors","Wireless"],"lifecycle":[{"event":"open","at":"2026-09-24T14:44:02Z"}],"liveness":{"score":3,"band":"cold","label":"Long shot","p_open":1,"p_active":0.095,"p_room":0.28,"age_days":349,"expected_fill_days":22,"reasons":["conf:1","win:tail","crowd:brand"],"computed_at":"2026-09-25T03:46:50Z"},"pay":null,"html_url":"https://alion.io/job/mediatek-ip-dft-engineer","json_url":"https://alion.io/job/mediatek-ip-dft-engineer.json","meta":{"generated_at":"2026-09-25T03:46:50Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4111,"day_limit":5000,"remaining_today":889,"minute_limit":60,"resets_at":"2026-09-26T00:00:00Z"}}}