{"id":1185286,"url":"https://alion.io/job/mediatek-rtl-design-lead","title":"RTL Design Lead","company":{"id":62191,"name":"MediaTek","domain":"mediatek.com","url":"https://alion.io/company/mediatek","size_band":"1001-5000","is_staffing_agency":false,"is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":37000,"max_usd":89000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":344},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-08-23T16:00:00Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-09-25T02:30:43Z","board_verified":true,"closed_at":null,"days_open":32,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":32},"description":"Design Lead works with hardware engineering teams to build complex chips, System-on-Chips (SoCs), and IP/Sub-system blocks.Guides microarchitecture definition, RTL design, verification, and physical implementation from conception through tape-out, balancing power, performance, area, and schedule goals.\nKey Responsibilities\nExecution & Delivery: Drive end-to-end design development of IP/Sub-system blocks and SoCs to meet the Performance, Area, Power and Schedule targets.\nTeam Leadership: Manage, mentor, and set goals for a team of digital engineers involved in design, synthesis, and timing.\nPPA Optimization: Oversee design reviews to optimize Power, Performance, and Area (PPA) metrics.\nCross-Functional Collaboration: Partner with architecture, verification, and physical design teams.\nSign-off & Debug: Drive resolution on complex bugs, logic issues, and sign-off checks.\nCore Technical Skills\nDesign Languages: Advanced proficiency in Verilog, System-Verilog, and scripting tools like Python or Perl.\nArchitecture Knowledge: Familiarity with ARM or RISC-V processors, bus protocols (AXI/AHB), and high-speed interfaces (PCIe, USB, DDR).\nSign-off Methodologies: Experience with Static Timing Analysis (STA), Clock Domain Crossing (CDC), and Logical Equivalence Checking (LEC).","description_format":"text","description_chars":1285,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Semiconductors","Wireless"],"lifecycle":[{"event":"open","at":"2026-09-24T14:44:02Z"}],"liveness":{"score":51,"band":"ok","label":"Likely open","p_open":1,"p_active":0.679,"p_room":0.75,"age_days":32,"expected_fill_days":33,"reasons":["conf:1","win:late","comp:brand"],"computed_at":"2026-09-25T04:10:59Z"},"pay":null,"html_url":"https://alion.io/job/mediatek-rtl-design-lead","json_url":"https://alion.io/job/mediatek-rtl-design-lead.json","meta":{"generated_at":"2026-09-25T04:10:59Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4541,"day_limit":5000,"remaining_today":459,"minute_limit":60,"resets_at":"2026-09-26T00:00:00Z"}}}