{"id":1185482,"url":"https://alion.io/job/mediatek-senior-ip-design-engineer","title":"Senior IP Design Engineer","company":{"id":62191,"name":"MediaTek","domain":"mediatek.com","url":"https://alion.io/company/mediatek","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"C","score":63,"open_postings":353,"ghost_share":0.623,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-01T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":124000,"max_usd":233000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":910},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-04-06T16:00:00Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-09-28T11:17:46Z","board_verified":false,"closed_at":null,"days_open":177,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":177},"description":"MediaTek is a leading global fabless semiconductor company powering more than 2 billion devices a year. Our cutting-edge system-on-chip solutions enable some of the world’s most popular smartphones, smart TVs, connectivity products, IoT devices, and more. We combine deep engineering expertise with a collaborative, fast-paced work environment where innovation, curiosity, and teamwork drive everything we do.About the Role\nMediaTek is seeking a motivated Senior IP Design Engineer interested in architectural modeling and digital design for Dynamic Voltage & Frequency Scaling (DVFS) IP. In this role, you will build high-level architectural models for DVFS IP to evaluate new architectures and features; identify system-level performance bottlenecks and explore design trade-offs; develop quality digital designs using SystemVerilog RTL based on architectural specifications; conduct RTL signoff checks and collaborate with physical design teams on performance optimization. You will gain the opportunity to develop state-of-the-art power and performance management used in High-Performance Compute (HPC) products, including the design of clock delivery networks (CDN) and power delivery networks (PDN) for modern CPU/GPU/NPU.\nKey Responsibilities\n1. Architectural Modeling: Build high-level architectural models to evaluate new architectures, features, and design trade-offs before RTL implementation.\n2. Digital Design Development: Create quality digital designs using SystemVerilog RTL that meet the computational functions or control sequences specified in the design specifications.\n3. Conduct RTL sign-off checks, including LINT, CDC, & CLP.\n4. Co-work with verification teams for block-level and system-level verification\n5. Supply necessary collateral for physical design, including SDC/UPF, and collaborate with the physical design team for timing critical path and power analysis.","description_format":"text","description_chars":1892,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless Hardware","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-24T14:44:02Z"}],"liveness":{"score":6,"band":"cold","label":"Long shot","p_open":0.9,"p_active":0.249,"p_room":0.28,"age_days":177,"expected_fill_days":30,"reasons":["conf:66","stale_co","velocity","ghost","win:tail","crowd:brand"],"computed_at":"2026-10-01T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/mediatek-senior-ip-design-engineer","json_url":"https://alion.io/job/mediatek-senior-ip-design-engineer.json","meta":{"generated_at":"2026-10-01T11:24:49Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":3077,"day_limit":5000,"remaining_today":1923,"minute_limit":60,"resets_at":"2026-10-02T00:00:00Z"}}}