{"id":1185232,"url":"https://alion.io/job/mediatek-seniorstaff-digital-design-engineer","title":"Senior/Staff Digital Design Engineer","company":{"id":62191,"name":"MediaTek","domain":"mediatek.com","url":"https://alion.io/company/mediatek","size_band":null,"is_staffing_agency":false,"is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Cairo, Egypt"],"countries":["EG"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":78000,"max_usd":169000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":754},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-09-17T16:00:00Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-09-24T22:49:28Z","board_verified":true,"closed_at":null,"days_open":7,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":7},"description":"MediaTek Egypt is seeking a skilled and motivated digital design engineer to join our high-performance team focusing on SerDes and high-speed interface IP development. The successful candidate will be responsible for the architecture, RTL design, and integration of PHY IP blocks, collaborating with cross-functional teams to ensure high-quality and robust IP solutions for cutting-edge SoCs.Key Responsibilities:\n1. PHY IP Architecture Planning\nContribute to the architectural design of PHY IPs for high-speed interfaces such as Ethernet SerDes, USB, PCIe, HDMI, DisplayPort, MPHY, and CPHY.\n2. RTL Design & Coding\nDevelop and implement RTL code for PHY IPs with a focus on performance, power efficiency, and silicon area optimization.\n3. Front-end and Back-end Integration\nHandle the integration of PHY IPs in both front-end and back-end design flows, ensuring seamless connectivity and function within the SoC.\n4. Cross-functional Collaboration\nWork closely with MAC design and Design Verification (DV) teams for system-level IP verification.\nCollaborate with analog design teams for PHY/SerDes co-simulation and mixed-signal integration.","description_format":"text","description_chars":1141,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Semiconductors","Wireless"],"lifecycle":[{"event":"open","at":"2026-09-24T14:44:02Z"}],"liveness":{"score":80,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.796,"p_room":1,"age_days":7,"expected_fill_days":31,"reasons":["conf:2","win:early","comp:brand"],"computed_at":"2026-09-25T01:11:38Z"},"pay":null,"html_url":"https://alion.io/job/mediatek-seniorstaff-digital-design-engineer","json_url":"https://alion.io/job/mediatek-seniorstaff-digital-design-engineer.json","meta":{"generated_at":"2026-09-25T01:11:38Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":1145,"day_limit":5000,"remaining_today":3855,"minute_limit":60,"resets_at":"2026-09-26T00:00:00Z"}}}