{"id":4270205,"url":"https://alion.io/job/mercor-design-verification-engineer-fully-remote-upto-175hr","title":"Design Verification Engineer - Fully Remote | Upto $175/hr","company":{"id":4960,"name":"Mercor","domain":"mercor.com","url":"https://alion.io/company/mercor","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":true,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"A","score":87,"open_postings":14,"ghost_share":0,"stale_share":0.286,"repost_share":0.071,"time_to_fill_p50_days":77,"computed_at":"2026-11-14T05:58:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"contractor","work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"inferred_payroll_markers","remote_working_hours":null,"hiring_geo_confidence":"inferred","locations":[],"countries":[],"hiring_countries":["CA"],"hiring_countries_total":1,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"LLM","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-11-13T16:53:05Z","employer_posted_date":null,"last_verified_at":"2026-11-13T16:53:05Z","board_verified":false,"closed_at":null,"days_open":1,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":1},"description":"About the jobMercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark, General Catalyst, Peter Thiel, Adam D'Angelo, Larry Summers, and Jack Dorsey.\nPosition: RTL Design Engineers\nType:Contract\nCompensation:$100–$175/hour\nLocation:Remote\nDuration:3+ months\nCommitment:40 hours/week\nRole Responsibilities\nEvaluate digital chip design workflows to enhance AI model training and evaluation.\n\nDesign and verify RTL components using Verilog/SystemVerilog.\n\nCollaborate with architecture, verification, and implementation teams to improve model outputs.\n\nDevelop reusable verification components and testbench infrastructure.\n\nLeverage LLM-based tools to accelerate chip design and verification processes.\n\nWork independently and asynchronously to meet project deadlines.\n\nQualifications\nMust-Have\n\n3–10 years of experience in digital RTL design or design verification.\n\nStrong proficiency in Verilog/SystemVerilog and UVM.\n\nSolid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols.\n\nExperience with ASIC design flows and common EDA tools.\n\nAbility to write clear design documentation and communicate technical tradeoffs.\n\nPreferred\nKnowledge of AMBA protocols (AXI, AHB, APB).\n\nBackground in CPU, GPU/ML accelerator, networking, memory subsystem, PCIe/high-speed IO, SoC interconnect, low-power design.\n\nExposure to formal verification or SV/UVM-based design verification.\n\nStart DateWeek of 04/23; applications reviewed on a rolling basis.\nCompensation & LegalHourly contractor, Paid weekly.\nApplication Process (Takes 20–30 mins to complete)\nUpload resume\n\nAI interview based on your resume\n\nSubmit form\n\nResources & Support\nFor details about the interview process and platform information, please check: \n\nFor any help or support, reach out to: \n\nPS: Our team reviews applications daily. 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