ASIC Engineer, Design

The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing with superior capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains.

Responsibilities

Architecture exploration Micro-architecture development Soft and hard IP identification, selection and integration Collaboration with verification and emulation teams in test plan development and debug Collaboration with implementation team to close the design on timing and power

Qualifications

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of silicon development experience with experience of first-pass success in ASIC (Application-Specific Integrated Circuit) Development Experience in one of these skills: Micro-architecture and RTL development for complex control and data path IPs (Intellectual Properties), OR Experience in SoC (System on Chip) Micro-architecture, Design and Integration, OR Implementation, Power methodology development Experience with Verilog or System Verilog Lint, CDC (Clock Domain Crossing), Synthesis and Power Optimization Experience working across multiple projects Experience with scripting languages (TCL, Python, Perl, Shell-scripting) Experience in CPU, NOC (Network on Chip), Memory and Peripheral Subsystems Experience with Power Analysis and Optimization Experience in data path development Experience in HLS (High-Level Synthesis) Experience with Synthesis, Timing Closure and Formal Verification Methodology 15+ years of experience in silicon development