ASIC Engineer, Design
Confirmed on the employer's own hiring board on Oct 16, 2026. First seen by Alion on Sep 21, 2026. Meta scores B on the Alion truth index.
Responsibilities
Architecture exploration Micro-architecture development Soft and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and debug Collaboration with implementation team to close the design on timing and power
Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration RTL development using Verilog, System Verilog and HLS Experience in CPU, NOC, Memory and Peripheral Subsystems Experience with Synthesis, Timing Closure and Formal Verification Methodology Master’s or PhD degree in Electrical Engineering, Computer Science or related areas Experience in data path development