{"id":2670480,"url":"https://alion.io/job/meta-asic-engineer-intern-design-verification","title":"ASIC Engineer Intern, Design Verification","company":{"id":20,"name":"Meta","domain":"meta.com","url":"https://alion.io/company/meta","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career sitemap","truth_index":{"grade":"B","score":80,"open_postings":238,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":14,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"intern","employment_type":"internship","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":76000,"period":"year","method":null,"sample_n":3689},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-10-14T05:59:39Z","employer_posted_date":"2026-10-14","last_verified_at":"2026-10-17T20:00:48Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Meta is seeking an ASIC Engineer Intern to join our Infrastructure organization. Our servers and data centers are the foundation upon which our rapidly scaling infrastructure efficiently operates and upon which our services are delivered. By holding this role, you will be an integral member of an ASIC team to build accelerators for some of our top workloads enabling our data centers to scale efficiently. You will have an opportunity to participate in design and verification of advanced IPs using state of the art tools. Come work and learn alongside our ASIC engineers to build “Green” data center accelerators.Internships are twelve (12) to sixteen (16) weeks long.\nResponsibilities\nDevelop tests, checkers and coverage to help verify designs. Develop understanding of the architecture and microarchitecture of designs. SystemVerilog/UVM/C code to generate test content. Develop scripts to automate various processes. Debug test failures, work with design, verification and modeling teams to fix and verify the fixes. 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