{"id":3711804,"url":"https://alion.io/job/meta-design-verification-engineer-accelerators","title":"Design Verification Engineer - Accelerators","company":{"id":20,"name":"Meta","domain":"meta.com","url":"https://alion.io/company/meta","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career sitemap","truth_index":{"grade":"B","score":77,"open_postings":249,"ghost_share":0,"stale_share":0.924,"repost_share":0,"time_to_fill_p50_days":37,"computed_at":"2026-11-06T05:58:05Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Computer Vision","optional":false},{"name":"Formal Verification","optional":false},{"name":"Machine Learning","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-11-03T18:52:51Z","employer_posted_date":"2026-11-03","last_verified_at":"2026-11-06T05:32:20Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"The AR glasses Meta is building run on custom silicon that delivers serious compute within a tight power budget. Our silicon team designs that silicon, with breakthrough work in computer vision, machine learning, imaging, and sensing. We're hiring a Design Verification (DV) lead to own verification for complex computer vision and imaging accelerator IP and subsystems. In this role, you'll define the verification strategy across multiple IPs and build DV infrastructure that scales across chips and programs.Responsibilities\nShape architecture and microarchitecture decisions with architects, design, FW/SW, emulation, physical design and post-silicon teams so the chip is designed with verification in mind. Work with TPMs on schedules and sign-off criteria Own DV for multiple complex IPs or subsystems from start to finish, all the way from verification planning through coverage closure and sign-off Define the strategy across IPs, including the mix of simulation (constrained-random, UVM), formal, assertions, emulation and FPGA prototyping, plus power-aware verification (UPF) Design reusable testbench architectures, verification IP and libraries that are shared across IPs, subsystems and SoC generations Drive regression management, automated triage, coverage analytics, and compute-efficient runs (simulation and emulation) so the team can sustain high throughput as the number of designs grows Spot verification-quality and productivity gaps across the org, lead initiatives that measurably improve quality and time-to-closure, and drive DV methodology improvements, including AI-assisted ones Root-cause failures down to specific lines of RTL, reference model or FW/SW, and propose the fixes\nQualifications\nBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience 8+ years of hands-on verification experience with SystemVerilog, UVM and C/C++ at the IP, subsystem and SoC level Has led DV for complex IP or an SoC through tape-out, including owning sign-off Has defined and run verification plans, coverage strategies, and closure metrics (functional and code coverage) across multiple blocks or IPs Has built UVM verification environments from scratch and designed reusable verification components Deep experience in at least one of: formal verification, SystemVerilog Assertions (SVA), emulation/FPGA prototyping, or low-power (UPF) verification Strong scripting skills (Python, TCL, Perl, Shell) for building verification tools and flows Has led and mentored engineers and coordinated work across teams Has verified power-limited mobile, wearable or AR/VR System-on-Chips (SoCs) Has managed EDA vendors or contracted DV teams Has verified computer vision, imaging/ISP, DSP or ML accelerator designs Master's or PhD in EE/CE/CS Has rolled out methodology changes (formal, emulation, portable stimulus, ML/AI-assisted verification) across an org Has verified hardware against reference models written in C++ or Python, or co-simulated with firmware or software Has scaled DV infrastructure (regression farms, CI for hardware, coverage and triage dashboards) across multiple IPs or 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