DPU Power Architect, Infrastructure Silicon

We are seeking an experienced Power Architect to drive power modeling, analysis, and architectural power optimization of our Data Processing Unit (DPU) designs. In this role you will influence architecture and microarchitecture decisions from early path-finding through RTL/gate-level power analysis and silicon correlation, ensuring our DPUs deliver leading performance-per-watt on real data center workloads.

Responsibilities

Analyze and characterize real-world DPU software use cases (network virtualization, storage offload, crypto/compression, packet processing) to identify hardware power bottlenecks and power-relevant behaviors Build and maintain workload-driven, system-level power models and power rollups for current and future SmartNIC/IPU/DPU architectures, tracking accuracy from early analytical estimates through RTL and gate-level power analysis Quantify architectural and micro-architectural trade-offs with respect to PPA, with emphasis on energy-per-transaction, power-per-bit moved, and performance-per-watt, to inform and guide design decisions Define and drive structural power-saving architecture features, including DVFS, AVS, power gating, clock gating, activity throttling, power state management, and workload-aware power policies Analyze SoC pipelines and data movement paths (host-to-DPU, memory/fabric/network traffic) to understand and optimize the power-versus-performance trade-off Own power budgets and provide power-delivery and thermal inputs in partnership with design, physical design, firmware, platform, and software teams Correlate pre-silicon power projections with post-silicon measurements and drive methodology improvements based on findings

Qualifications

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience Experience in workload analysis and characterization, and abstracting power-relevant behaviors into models for architectural analysis Experience building system-level power models and power rollups, and tracking them from early estimates through RTL/gate-level power Experience defining or evaluating architectural power-saving features such as DVFS, power gating, and clock gating Understanding of SoC pipelines and how data movement impacts power versus performance Proficiency in programming languages for model development and automation (e.g., Python, C/C++, SystemC) Experience driving analysis independently and influencing architectural direction through data PhD in Computer Science, Computer Engineering or Electrical Engineering 15+ years of relevant industry experience in power architecture and power modeling for high-performance SoCs Experience with power management firmware/software co-design, on-die power telemetry, and closed-loop power/thermal control Experience with simulation/emulation environments used in ASIC development flows, including emulation-based activity capture (FSDB/SAIF) for long-window power analysis Experience with low-power implementation flows, including multi-voltage/UPF power intent, retention and isolation strategies Experience building or scaling power modeling and power regression infrastructure for hyperscale data center ASICs (network, storage, or AI accelerator designs) Familiarity with post-silicon power measurement, telemetry, and model-to-hardware correlation methodologies Experience with industry-standard power estimation and sign-off tools (e.g., Synopsys PrimePower/PTPX, Cadence Joules, Ansys PowerArtist) for power analysis and optimization Familiarity with power delivery network, voltage droop/di-dt analysis, and rack/platform-level power and thermal constraints