Machine Learning Hardware Architect - Silicon

Reality Labs (RL) focuses on delivering Meta's vision through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. Reality Labs Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.

In this position you will work with Machine Learning Hardware Architects, Digital Designers, and Software engineers to develop custom Machine Learning Hardware accelerators for delivery into multiple SoCs. You will collaborate with a world-class group of researchers and architects to implement and contribute to the development and optimization of low power machine learning accelerators and state-of-the-art SoCs.

Responsibilities

Technical lead for ML Hardware engineers, driving design from Architecture through to Product for AR/VR optimized silicon Lead designs to surpass state of the art for metrics such as compute, bandwidth, and power consumption Work across disciplines, brainstorm big ideas, work in new technology areas, juggle/coordinate multiple initiatives, drive a concept into a prototype and ultimately guide the transition into a high-volume consumer product Travel both domestically and internationally

Qualifications

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 12+ years of experience as a Hardware Design Engineer or Silicon Architect for production silicon shipped in volume Experience in Machine Learning IPs Silicon development Experience in digital design µArchitecture, RTL coding Experience with methods for partitioning a solution across hardware and software, evaluating trade-offs such as speed, performance, power, area Results oriented, proactive with demonstrated creative & critical thinking Master/PhD degree in EE/CS or equivalent areas Knowledge of Physical Design and Low power implementation Experience with Firmware, DSP coding and optimization Collaborate and/or lead in a team environment Experience with SoC Architecture and subsystem Integration Knowledge of industry trends and disruptive technologies Experience in deep learning algorithms and techniques, e.g., convolutional neural networks, transformers, LLMs