{"id":3307454,"url":"https://alion.io/job/microchip-technology-engineer-ii-verification-2","title":"Engineer II - Verification","company":{"id":44188,"name":"Microchip Technology","domain":"microchip.com","url":"https://alion.io/company/microchip","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":75,"open_postings":111,"ghost_share":0,"stale_share":0.982,"repost_share":0,"time_to_fill_p50_days":29,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Chandler, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":83000,"max_usd":159000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":664},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"UVM","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"SystemVerilog","optional":true}],"status":"live","first_seen_at":"2026-10-26T00:00:00Z","employer_posted_date":"2026-10-26","last_verified_at":"2026-10-30T23:28:56Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognizedLeadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\nVisit our careers page to see what exciting opportunities and company perks await!\nJob Description:\nJoin the dsPIC Microcontroller Business Unit, IP Verification Engineering team as Engineer II-Verification, doing IP level verification, testbench architecture, modeling, simulation, coverage, regression, formal or dynamic simulation (UVM tests), debugging, signoff evidence, and lifecycle support. This role is best suited for candidates with 2.5-5 years of relevant experience in IP design verification, testbench architecture, modeling, simulation, coverage, regression, formal or dynamic simulation, debugging, signoff evidence, and lifecycle support.\nIn this role, you will independently execute defined assignments and structured troubleshooting, partner with cross-functional teams (architecture, design, product development , validation, and application) across the USA, India, and other global corporate teams to deliver robust verification results, timely project execution, and continuous improvement.\nResponsibilities:\nArchitect, develop, and maintain UVM based verification environments and/or Formal verification environments.\nCollaborate with architecture, designer, validation, and applications teams to verify IP and product requirements.\nDevelop and maintain verification plans, test strategies and testbenches.\nDevelop constraint random tests and testbench, assertions and coverage, analyze coverage metrics and drive coverage closure.\nDevelop Formal properties, analysis proof results and drive Formal coverage closure.\nConfigure, execute, and maintain UVM simulation and/or Formal regressions.\nDebug failures in RTL and testbench, perform root-cause analysis, and collaborate with design and architecture teams to resolve the defects.\nLeverage AI-assisted and machine-learning based automation to improve verification quality, accelerate development and debugging, and reduce verification cycle time.\nRequirements/Qualifications:\nMinimum qualifications\nBachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, Engineering, or a related field with 2.5-5 years of relevant experience in design verification, UVM and/or Formal testbench architecture, modeling, simulation, coverage, regression, debugging, signoff evidence, and lifecycle support.\nQualified candidates should demonstrate verification architecture, modeling, and simulation, UVM and Formal testbench development, coverage analysis, structured debugging, AI/ML automation, technical documentation, and cross-functional influence.\nSuccessful candidates are expected to demonstrate:\nEmployment stability, reliability, and sustained accountability in prior roles.\nEffective teamwork and cross-functional collaboration.\nIntegrity and accuracy in representing qualifications, experience, and credentials.\nPreferred Qualifications:\nHands-on experience with UVM-based simulation and/or Formal verification methodologies and tools.\nStrong proficiency in System Verilog language, constrained-random verification, assertions, and coverage.\nExperience developing and maintaining IP level and SoC level verification environments.\nExperience with simulation, regression execution, coverage analysis, debug, verification signoff, and lifecycle support.\nExperience with verification automation and scripting using Python or Perl.\nExperience with AI assisted technologies to improve verification productivity, quality, and driver faster coverage closure.\nStrong understanding of digital design concepts, RTL fundamentals, and ARM or common SoC architectures.\nTravel Time:\n0% - 25%Physical Attributes:\nHearing, Seeing, Talking, Works Alone, Works Around OthersPhysical Requirements:\n80% Sitting, 10% Walking, 10% StandingMicrochip Technology Incis an equal opportunity/affirmativeaction employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.\nFor more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. 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