{"id":2894684,"url":"https://alion.io/job/microchip-technology-principal-engineer-design-2","title":"Principal Engineer -Design","company":{"id":44188,"name":"Microchip Technology","domain":"microchip.com","url":"https://alion.io/company/microchip","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":75,"open_postings":104,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":28,"computed_at":"2026-10-26T05:57:25Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Saskatoon, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":66000,"max_usd":121000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":107},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Genus","optional":false},{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-08-12T00:00:00Z","employer_posted_date":"2026-08-12","last_verified_at":"2026-10-27T02:05:01Z","board_verified":true,"closed_at":null,"days_open":76,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":76},"description":"Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognizedLeadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\nVisit our careers page to see what exciting opportunities and company perks await!\nJob Description:\nMicrochip’s Communications Business Unit (CBU) is a premier supplier of 100Gbps+ Optical Networking and Connectivity Solutions for Telecom and Hyperscale Data Center Networks. Our state-of-the-art devices power high-bandwidth, cloud-based applications including streaming services, social media platforms, and video conferencing worldwide.\nThe CBU Product Development team drives the full semiconductor R&D lifecycle-from initial concept, design, and implementation to embedded software integration, system validation lab testing, and mass-market production release. Working with the latest tools and methodologies in advanced process nodes, our experienced team delivers industry-leading network devices.\nWe are seeking a Principal Engineer to join the CBU Product Development team. In this role, you will lead the digital design, DFT, physical implementation, and static timing analysis (STA) of integrated circuits at both the block and top chip levels.\nWorking alongside our implementation team on advanced technology nodes, you will drive RTL-to-pre-layout netlist generation and own STA signoff across multiple macros, subsystems, and full-chip designs using industry-standard Cadence and Synopsys synthesis suites.\nResponsibilities:\nResponsible to develop macro constraints (Synthesis, STA & Layout), ram generations, flow configuration for High-speed complexmacrosand Subsystems.\n\nResponsible for STA sign off for all levels of design hierarchy for multiple modes and multiple corners (MMMC)\n\nResponsible to develop/understand flow and methodology for doing RTL Synthesis.\n\nAbility topick upnew flows, learn on the job and influence QOR is a must.\n\nCo-work with RTL and DFT engineers and interact with project teams to ensure the right constraints/deliverables are in place.\n\nEnsure the Quality of deliverables pre/post netlists (CLP, LEC, In-house tool checks)\n\nClose interactions with APR team to ensure thatfloorplanning/macro placements/quality of deliverables are in the right direction.\n\nRequirements/Qualifications:\nQualification:\nBachelor’s or Graduate Degree in: Computer Sciences, Electrical/Electronics/VLSIEngineering\n\n10years of experience in synthesis, STA and Formal Verification with mainstream tools.\n\nExcellent analytical and debugging skills and the ability to proactively solve issues\n\nStrong coding skillsandscripting skills (TCL, Perl or Python).\n\nProven ability to thrive on, learn and adapt to new methodologies and technologies\n\nHands on experience in RTL Design, synthesis, low-power logic insertion using UPF/CPF and STA signoff of Macro’s and SoC Level.\n\nGood understanding of timing models, DFT, libs, hierarchical budgeting flows.\n\nHands-on to deliver solutions to critical design and execution issues related to synthesis.\n\nTapeoutexperience of 1 or more projectswith16nmorsmaller silicon process technologies\n\nHands-on experience with synthesis tools like Cadence Genus OR Synopsys-DC/FC.\n\nGood verbal and written communication skillsin English, strong interpersonal skills\n\nTravel Time:\n0% - 25%To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.","description_format":"text","description_chars":4753,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-10-20T04:12:14Z"}],"visa":[],"liveness":{"score":11,"band":"cold","label":"Long shot","p_open":1,"p_active":0.407,"p_room":0.28,"age_days":75,"expected_fill_days":28,"reasons":["conf:15","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-26T05:57:25Z"},"pay":null,"html_url":"https://alion.io/job/microchip-technology-principal-engineer-design-2","json_url":"https://alion.io/job/microchip-technology-principal-engineer-design-2.json","meta":{"generated_at":"2026-10-27T03:44:36Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":3190,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-28T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":44188},"rest":"https://alion.io/mcp/rest/get_company?id=44188"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fmicrochip-technology-principal-engineer-design-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fmicrochip-technology-principal-engineer-design-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fmicrochip-technology-principal-engineer-design-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/microchip-technology-principal-engineer-design-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fmicrochip-technology-principal-engineer-design-2"}]}