{"id":2877458,"url":"https://alion.io/job/microchip-technology-principal-engineer-design-fpga","title":"Principal Engineer- Design (FPGA)","company":{"id":44188,"name":"Microchip Technology","domain":"microchip.com","url":"https://alion.io/company/microchip","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":75,"open_postings":100,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":28,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Chandler, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":119000,"max_usd":226000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":609},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Git","optional":false},{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Siemens ModelSim","optional":false},{"name":"Siemens QuestaSim","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Xilinx Vivado","optional":false}],"status":"live","first_seen_at":"2026-08-19T00:00:00Z","employer_posted_date":"2026-08-19","last_verified_at":"2026-10-22T02:03:48Z","board_verified":true,"closed_at":null,"days_open":64,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":64},"description":"Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognizedLeadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\nVisit our careers page to see what exciting opportunities and company perks await!\nJob Description:\nMicrochip’s NCS Team is seeking an experienced FPGA Design Engineer to support PHY (Physical Layer) development and system-level solutions for our next generation of USB and Ethernet products. The role will involve working closely with digital, analog, and software engineers to develop, integrate, and validate FPGA-based platforms supporting mixed-signal IP and SoC products.\nThe candidate must be located in the Chandler Design Center.\nRequirements/Qualifications:\n10 years or more of experience in FPGA and/or digital design, with solid hands-on experience in RTL coding, simulation, synthesis, and hardware implementation.\n\nStrong proficiency in Verilog and/or SystemVerilog for synthesizable RTL design.\n\nStrong understanding of digital design fundamentals, including state machines, datapaths, pipelines, clocking, resets, FIFOs, memories, and interface logic.\n\nHands-on experience developing self-checking testbenches and performing functional simulation and debug using tools such as QuestaSim/ModelSim or equivalent simulation environments.\n\nHands-on experience with FPGA synthesis, implementation, timing analysis, and place-and-route using vendor design environments such as AMD/Xilinx Vivado.\n\nAbility to define and analyze timing constraints and experience designing systems containing multiple clock domains.\n\nExperience optimizing FPGA designs to achieve required performance, area/resource utilization, and target clock frequencies.\n\nExperience with FPGA system integration and board-level bring-up, including loading FPGA images, exercising hardware interfaces, and debugging designs on physical circuit cards.\n\nHands-on experience using laboratory debug equipment such as oscilloscopes, logic analyzers, protocol analyzers, and FPGA embedded logic-debug tools or equivalent.\n\nAbility to work closely with hardware, firmware, software, ASIC, analog, verification, and validation teams during system integration and lab bring-up.\n\nExperience in USB and Ethernet PHY architectures and protocols is a strong plus.\n\nProvide clear design documentation, including requirements, FPGA architecture, block diagrams and interface control documents.\n\nProficiency in scripting languages such as TCL, Python, Perl. Linux shell programming or programming languages such as C++ or RUST for automating FPGA build, simulation, synthesis, and implementation flows.\n\nKnowledge of revision-control systems such as Perforce, Git, DesignSync, or equivalent, including experience with tagging, branching, configuration management, and release methodologies.\n\nMust possess strong verbal and written communication skills and be able to participate effectively in technical discussions and design reviews, provide project updates, and develop functional and technical documentation.\n\nTravel Time:\n0% - 25%Physical Attributes:\nFeeling, Hearing, Seeing, Talking, Works Alone, Works Around OthersPhysical Requirements:\n80% sitting, 10% standing, 10% walkingMicrochip Technology Incis an equal opportunity/affirmativeaction employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.\nFor more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.","description_format":"text","description_chars":5142,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-10-19T21:52:07Z"}],"visa":[],"liveness":{"score":16,"band":"cold","label":"Long shot","p_open":1,"p_active":0.46,"p_room":0.35,"age_days":64,"expected_fill_days":28,"reasons":["conf:4","stale_co","velocity","win:tail","comp:brand"],"computed_at":"2026-10-22T06:10:10Z"},"pay":null,"html_url":"https://alion.io/job/microchip-technology-principal-engineer-design-fpga","json_url":"https://alion.io/job/microchip-technology-principal-engineer-design-fpga.json","meta":{"generated_at":"2026-10-22T10:46:43Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":8179,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-23T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":44188},"rest":"https://alion.io/mcp/rest/get_company?id=44188"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fmicrochip-technology-principal-engineer-design-fpga"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fmicrochip-technology-principal-engineer-design-fpga"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fmicrochip-technology-principal-engineer-design-fpga"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/microchip-technology-principal-engineer-design-fpga\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fmicrochip-technology-principal-engineer-design-fpga"}]}