{"id":1179262,"url":"https://alion.io/job/micron-technology-principal-asic-design-engineer","title":"Principal ASIC Design Engineer","company":{"id":37,"name":"Micron Technology","domain":"micron.com","url":"https://alion.io/company/micron-technology","size_band":"5000+","is_staffing_agency":false,"is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":79,"open_postings":767,"ghost_share":0,"stale_share":0.832,"repost_share":0,"time_to_fill_p50_days":25,"computed_at":"2026-09-24T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Boise, United States","Folsom, United States","Richardson, United States","San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":156000,"max_usd":302000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":251},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Genus","optional":false},{"name":"Cadence Innovus","optional":false},{"name":"Cadence JasperGold","optional":false},{"name":"Cadence Xcelium","optional":false},{"name":"Synopsys Design Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Synopsys SpyGlass","optional":false},{"name":"Synopsys VC Formal","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-09-24T12:42:41Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-09-24T17:48:17Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\nPrincipal ASIC Design Engineer\nAbout the Role\nAt Micron, we transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing.\nMicron’s Interface Pathfinding team drives performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3-5 year technology horizon. A core part of that work is silicon-based validation of novel PHY solutions, and we are growing the team to execute.\nAs the Principal ASIC Design Engineer, you will be the primary digital contributor on a deliberately small, senior team - united around the goal of carrying high-speed interface technologies from architecture to tape-out. The team’s analog and chip-level architecture is anchored by a deeply experienced analog custom design engineer; your role is to be the authoritative digital voice - owning RTL design and micro-architecture of the digital blocks, defining timing constraints, supporting verification, and serving as the key interface between the digital design and the analog and layout specialists who will carry the implementation through to silicon. On a test ASIC of this scope, the front-end digital work is the critical path, with contractor and layout support engaged as bandwidth demands warrant.\nWhat You’ll Own\nDigital Block Architecture & RTL Design\nOwn the micro-architecture and RTL implementation of all digital soft IP blocks - CSR/register file, clocking control logic, management bus interfaces, and control state machines - in synthesizable SystemVerilog.\nDefine and document block-level architecture specifications and interface control documents; serve as the authoritative reference for digital design intent.\nDefine CDC strategy for digital blocks and ensure clean closure using standard analysis tools.\nCoordinate with the analog design lead on top-level chip integration, analog/digital partitioning, and chip boundary interface definitions.\nSynthesis & Timing\nExecute logic synthesis (Synopsys Design Compiler or Cadence Genus) and drive optimization toward PPA targets.\nDevelop and maintain block-level SDC constraints; execute and close static timing analysis (PrimeTime or Tempus) across required corners and modes.\nPhysical Design Interface\nServe as the primary digital interface to the layout and implementation team - providing synthesized netlists, SDC constraints, floorplan guidance, and design intent documentation to enable effective physical implementation.\nReview and provide feedback on floorplan decisions, placement constraints, and timing closure results; partner with layout specialists to resolve implementation issues rooted in RTL or constraints.\nCoordinate with the verification team on scan chain insertion, DFT strategy, and ATPG planning.\nWhere bandwidth and experience allow, participate directly in place-and-route and physical verification flows.\nSelf-Verification & Verification Support\nSelf-verify RTL through block-level simulation (VCS or Xcelium), waveform debug (Verdi or DVE), and directed testing before engaging the verification team.\nWrite SystemVerilog Assertions (SVA) for critical control sequences and protocol compliance.\nCollaborate with the Design Verification Engineer on the block-level verification plan, testbench coverage, and bug resolution.\nSupport GLS and timing simulation using released netlists and SPF/parasitics; assist lab bring-up with simulation waveforms and register-level debug.\nDocumentation\nMaintain block specifications, SDC rationale, implementation guidance, and ECO history as institutional knowledge for follow-on chip development.\nWhat You Bring\nRequired\nBS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field\n7-12 years of ASIC design experience with at least one complete front-to-back tape-out\nProficiency in synthesizable SystemVerilog RTL design - linting-clean, well-documented coding practices\nHands-on experience with logic synthesis (Design Compiler or Genus) and static timing analysis (PrimeTime or Tempus)\nProficiency with RTL simulation and debug tools (VCS or Xcelium; Verdi or DVE) for block-level self-verification\nSolid understanding of CDC analysis methodologies (SpyGlass, JasperGold CDC, or equivalent)\nAbility to work effectively at the interface between digital design and custom/analog implementation teams - translating design intent into actionable guidance for layout and implementation specialists\nStrong written communication skills - this role produces specifications and documentation, not just code\nProficiency in leveraging AI tools for productivity across design, debug, and documentation workflows\nPreferred\nExperience working within a custom mixed-signal design team - comfortable operating alongside analog designers, layout engineers, and characterization specialists as a collaborative peer\nHands-on experience with place-and-route (Cadence Innovus or equivalent) and physical verification sign-off (Mentor Calibre) - candidates with full front-to-back implementation experience are strongly encouraged to apply\nExperience with mixed-signal or PHY-adjacent chip implementation - analog/digital partitioning, analog supply isolation, mixed-signal physical integration\nFamiliarity with high-speed PHY architectures (SerDes, DDR, or equivalent)\nFamiliarity with digital infrastructure for observability and silicon characterization - including PRBS generators, error counters, monitor interfaces, debug registers, and support for first silicon bring-up\nFamiliarity with I2C management bus, Eye Monitor control logic, or PRBS-based error counting\nFamiliarity with DFT methodologies - scan insertion, ATPG planning, boundary scan\nExperience with GLS flows using Liberty models and SPF parasitics\nFamiliarity with formal property verification (JasperGold or VC Formal)\nPrior experience in a small team or startup-like environment\nWhy This Role\nDeep digital ownership - from RTL architecture through synthesis, timing, and handoff to implementation - on a scope where your decisions are visible and your contributions immediately felt.\nYou will work alongside world-class engineers - a team of genuine collaborators.\nThe lean, senior team structure means your judgment is trusted and this is an individual contributor role with real impact.\nStrong execution here creates a clear path to expanded scope and follow-on programs of increasing complexity.\nA Note to All Candidates\nWe are building a long-term, high-caliber team around a compelling PHY technology program - and looking for engineers who want to own something, build something, and grow with a program. If that description resonates, we’d like to hear from you.\nThe US base salary range that Micron Technology estimates it could pay for this full-time position is:\n$186,000.00 - $407,000.00 a yearAdditional compensation may include benefits, bonuses and equity.\nOur salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. \nPlease note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.\nAs a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays.For additional information regarding the Benefit programs available, please see the Benefits Guide posted onmicron.com/careers/benefits.\nMicron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status,disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.\nTo learn about yourright to work click here.\nTo learn more about Micron, please visit micron.com/careers\nUS Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at  or 1-800-336-8918 (select option #3)\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\nAI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.","description_format":"text","description_chars":10340,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity","Parental leave"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Consumer Electronics","Hardware","Manufacturing","AI Infrastructure"],"lifecycle":[{"event":"open","at":"2026-09-24T12:42:41Z"}],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":25,"reasons":["conf:3","win:early","comp:brand"],"computed_at":"2026-09-24T21:06:49Z"},"pay":null,"html_url":"https://alion.io/job/micron-technology-principal-asic-design-engineer","json_url":"https://alion.io/job/micron-technology-principal-asic-design-engineer.json","meta":{"generated_at":"2026-09-24T21:06:49Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers"}}