{"id":3674120,"url":"https://alion.io/job/micron-technology-principal-engineer-sram-design","title":"Principal Engineer, SRAM Design","company":{"id":37,"name":"Micron Technology","domain":"micron.com","url":"https://alion.io/company/micron-technology","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":88,"open_postings":679,"ghost_share":0,"stale_share":0.49,"repost_share":0.007,"time_to_fill_p50_days":49,"computed_at":"2026-11-08T05:47:12Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India","Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys FineSim","optional":false},{"name":"Synopsys HSPICE","optional":false},{"name":"AI Agents","optional":true},{"name":"LLM","optional":true}],"status":"live","first_seen_at":"2026-11-03T10:11:24Z","employer_posted_date":"2026-11-03","last_verified_at":"2026-11-08T12:12:45Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\nMicron is seeking an experienced Principal SRAM Design Engineer to develop high-performance memory IP and testchip content for advanced semiconductor technologies.\nThe engineer will contribute towards architecture definition, transistor-level circuit design, simulations, and verifications.\nThe role requires strong hands-on knowledge of SRAM and bitcells, sense amplifiers, address decoders, control logic, etc.\nThe successful candidate will work closely with layout, CAD, process integration, testchip, and other partner teams to deliver robust, production-ready memory solutions.\nKey Responsibilities\nDesign, Develop and verify memory-array subsystems including bitcell arrays, precharge and equalization, sense amplifiers, write drivers, address decoders, wordline drivers, control logic, etc.\nEvaluate bitcell and peripheral-circuit stability, performance, leakage, dynamic power, and area across process, voltage, temperature, mismatch, and aging conditions.\nOwn transistor-level simulation and signoff using Spectre/FineSim, or comparable tools, including PVT corners, Monte Carlo analysis, parasitic-aware post-layout simulation, and waveform/debug reviews.\nPartner with layout engineers on floorplanning, bitcell-array composition, matching, critical-net routing, clock and control distribution, parasitic reduction, and layout-dependent effects.\nDevelop or improve automation for simulation setup, corner execution, results extraction, validation, and regression using Python, Tcl, Perl, SKILL, or similar languages.\nPlan and support SRAM testchips, including memory-instance selection, PPA objectives, test access, measurement structures, characterization plans, and alignment with process-learning goals.\nEngage process and foundry partners to understand device behavior, variation, layout restrictions, reliability constraints, and technology-specific opportunities affecting SRAM design margins.\nCreate clear circuit specifications, design-review material, verification plans and release documentation with traceable assumptions and decisions.\nMentor engineers on memory-circuit fundamentals, simulation discipline, PPA analysis, debug methods, and reusable design practices.\nExplore AI-assisted engineering workflows for specification extraction, circuit and block partitioning, test-mode enrichment, design-flow automation, regression analysis, and documentation while maintaining human technical review.\nTechnical Scope\nSRAM and register-file architectures, bitcell arrays, local and global datapaths, sensing, write paths, decoding, control, clocking, test access, and retention behavior.\nLow-power and high-performance design techniques including assist circuits, biasing, leakage reduction, dynamic-power optimization, robust low-voltage operation, and variation-aware sizing.\nMemory compilers and configurable macro generation, including architecture templating, legal configuration space, multi-view collateral, validation, and customer or SoC integration support.\nCircuit verification using spice simulators, PVT analysis, Monte Carlo mismatch, extracted post-layout simulation, and timing/power model correlation.\nTestchip development, silicon data analysis, debug, model calibration analysis, and process integration collaboration.\nMinimum Qualifications Demonstrated industry experience of 8+ yars in SRAM, register-file, ROM, DRAM peripheral, or other custom-memory circuit design.\nBS/MS/PhD in Electrical Engineering, Electronics, VLSI, Microelectronics, Computer Engineering, or a related field.\nStrong knowledge of CMOS transistor-level circuit design, memory architecture, static and dynamic timing behavior, power analysis, signal integrity, and process variation.\nHands-on experience with Cadence Virtuoso and SPICE-class simulators such as HSPICE, Spectre, or FineSim.\nExperience performing PVT-corner, Monte Carlo, parasitic-aware post-layout, and power/timing characterization analyses.\nAbility to translate product or testchip requirements into circuit architecture, measurable design targets, verification plans, and release criteria.\nExperience collaborating with layout, CAD, process/foundry, verification, product, and silicon characterization teams.\nClear technical communication, structured problem solving, and the ability to debug complex circuit or silicon issues using data and waveform evidence.\nPreferred Qualifications\nExperience developing low-power SRAM compilers or register-file compilers across multiple technology nodes and foundries.\nExperience with bitcell and peripheral circuit stability analysis, PPA aware design schemes, and memory validation.\nTrack record of taking memory IP from product definition and circuit design through layout, simulations, release, and silicon correlation.\nExperience planning memory testchips and partnering with silicon test teams on characterization, debug, and correlation.\nProficiency in Python, Tcl, Perl, SKILL, or similar languages for simulation, characterization, regression, and design-flow automation.\nFamiliarity with RTL-to-GDS or digital-on-top methodologies for memory periphery and control logic, alongside full-custom array and critical-circuit design.\nExperience applying agentic AI, coding assistants, or custom LLM agents to specification processing, design automation, validation, or engineering productivity.\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich lifefor all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities - from the data center to the intelligent edge and across the client and mobile user experience.\nTo learn more, please visit micron.com/careers\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\nTo request assistance with the application process and/or for reasonable accommodations,please \nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\nAI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.","description_format":"text","description_chars":7551,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Enterprise Storage Systems","Semiconductor Manufacturing","Memory & Storage Chips"],"lifecycle":[{"event":"open","at":"2026-11-03T10:11:24Z"}],"visa":[],"liveness":{"score":99,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.993,"p_room":1,"age_days":4,"expected_fill_days":49,"reasons":["conf:5","urgency","velocity","win:early","comp:brand"],"computed_at":"2026-11-08T05:47:12Z"},"pay":null,"html_url":"https://alion.io/job/micron-technology-principal-engineer-sram-design","json_url":"https://alion.io/job/micron-technology-principal-engineer-sram-design.json","meta":{"generated_at":"2026-11-08T22:16:42Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":46510,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-09T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":37},"rest":"https://alion.io/mcp/rest/get_company?id=37"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fmicron-technology-principal-engineer-sram-design"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fmicron-technology-principal-engineer-sram-design"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fmicron-technology-principal-engineer-sram-design"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/micron-technology-principal-engineer-sram-design\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fmicron-technology-principal-engineer-sram-design"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3674120}},{"tool":"search_jobs","arguments":{"company":"micron.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3674120},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}