{"id":2972711,"url":"https://alion.io/job/micron-technology-sr-engineer-ddeg-design-methodology-2","title":"SR ENGINEER, DDEG Design Methodology","company":{"id":37,"name":"Micron Technology","domain":"micron.com","url":"https://alion.io/company/micron-technology","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":85,"open_postings":848,"ghost_share":0,"stale_share":0.591,"repost_share":0.002,"time_to_fill_p50_days":42,"computed_at":"2026-10-21T05:46:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":20000,"max_usd":52000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Agentic Workflows","optional":false},{"name":"Synopsys HSPICE","optional":false},{"name":"Verilog","optional":false},{"name":"Python","optional":true},{"name":"SystemVerilog","optional":true},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2026-09-03T00:00:00Z","employer_posted_date":"2026-09-03","last_verified_at":"2026-10-21T07:15:37Z","board_verified":true,"closed_at":null,"days_open":48,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":48},"description":"Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\nUnique Opportunities\nComplete ownership of verification and end to end analysis of sophisticated full chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR4,LPDDR4,DDR5 and LPDDR5 that can operate at high speeds of up to 6400MT/s.\nCollaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design.\nWork on multi-functional tasks that can widen your skills.\nResponsibilities:\nActively leverage AI-based tools, agentic workflows, and automation frameworks to:\nAccelerate verification cycle time\nAssist in Test-Case/TB and various other components required for DRAM Design Verification\nImprove debug efficiency across simulation and silicon learning loops\n\nStrong judgment to validate AI outputs before use (review assumptions, align with specs/standards, cross-check with simulations, waveforms, assertions, and coverage reports, and document what was accepted/changed) prior to incorporating results into design decisions, verification plans, or debug conclusions\nProvide verification support to design projects by simulating, analyzing, and debugging pre-silicon block level/full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features.\nDevelop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products.\nGood understanding of digital / mixed signal circuits and experience in Digital /Mixed signal Verification. Understand the usage of tools like Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice.\nHands on experience in writing Verilog, Real Number Models is a plus.\nHands on experience in building SV testbenches at Block and Fullchip Level.\nHands on experience in SV, UVM based Verification. Good scripting skills using perl, python is a plus.\nPrevious work experience in DRAM memory related fields is a plus. Must possess good communication, debugging skills and ability to work well in a team.\nCore Requirements\nGood communication skills and ability to work well in a team\nGuide new team members and energetic engineers in the team\nAnalytical capability for complex CMOS and/or gate level circuit designs\nProficient with either SPICE and/or Verilog simulations\nQualifications & Skills\nExperience in SystemVerilog, PLI coding\nExperience in UVM Test Bench\nExperience in DRAM, SRAM or other memory related fields\nExperience in AMS verification and co-sim\nEducation\nBachelors or Post Graduate Degree in Electronics Engineering or related engineering field required\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich lifefor all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities - from the data center to the intelligent edge and across the client and mobile user experience.\nTo learn more, please visit micron.com/careers\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\nTo request assistance with the application process and/or for reasonable accommodations,please \nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\nAI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.","description_format":"text","description_chars":5183,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Enterprise Storage Systems","Semiconductor Manufacturing","Memory & Storage Chips"],"lifecycle":[{"event":"open","at":"2026-10-21T03:09:04Z"}],"visa":[],"liveness":{"score":33,"band":"fade","label":"Fading","p_open":1,"p_active":0.596,"p_room":0.55,"age_days":48,"expected_fill_days":42,"reasons":["conf:0","stale_co","urgency","velocity","win:tail","comp:brand"],"computed_at":"2026-10-21T05:46:15Z"},"pay":null,"html_url":"https://alion.io/job/micron-technology-sr-engineer-ddeg-design-methodology-2","json_url":"https://alion.io/job/micron-technology-sr-engineer-ddeg-design-methodology-2.json","meta":{"generated_at":"2026-10-21T07:25:28Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":10526,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-22T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":37},"rest":"https://alion.io/mcp/rest/get_company?id=37"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fmicron-technology-sr-engineer-ddeg-design-methodology-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fmicron-technology-sr-engineer-ddeg-design-methodology-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fmicron-technology-sr-engineer-ddeg-design-methodology-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/micron-technology-sr-engineer-ddeg-design-methodology-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fmicron-technology-sr-engineer-ddeg-design-methodology-2"}]}