{"id":3903115,"url":"https://alion.io/job/micron-technology-sram-design-lead","title":"SRAM Design Lead","company":{"id":37,"name":"Micron Technology","domain":"micron.com","url":"https://alion.io/company/micron-technology","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":88,"open_postings":679,"ghost_share":0,"stale_share":0.49,"repost_share":0.007,"time_to_fill_p50_days":49,"computed_at":"2026-11-08T05:47:12Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Boise, United States","Albany, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys FineSim","optional":false},{"name":"Synopsys HSPICE","optional":false},{"name":"Verilog","optional":false},{"name":"AI Agents","optional":true},{"name":"LLM","optional":true}],"status":"live","first_seen_at":"2026-11-06T00:00:00Z","employer_posted_date":"2026-11-06","last_verified_at":"2026-11-08T12:12:45Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\nOverview:\nMicron is seeking an experienced SRAM Design Engineer to develop high-performance, low-power embedded memory IP and testchip content. This is for advanced semiconductor technologies. The engineer will contribute across the complete memory-development lifecycle, including architecture definition, transistor-level circuit build, composing detailed circuit diagrams, layout interface, SPICE verification, timing and power characterization, compiler enablement, and pre- and post-silicon validation.\nThe role requires strong hands-on knowledge of SRAM and register-file design, memory arrays and bitcells, read/write datapaths, sense amplifiers, address decoding, control logic, assist techniques, and PPA tradeoffs. The candidate will work closely with teams handling layout development, CAD tools, manufacturing processes, testchip, product, silicon-test, and foundry. They will develop reliable, production-ready memory solutions and correlate models with measured silicon behavior.\nKey Responsibilities\nDesign and optimize custom SRAM, register-file, and embedded-memory circuits from architecture through schematic, layout support, characterization, and release.\nDevelop and verify memory-array subsystems including bitcell arrays, precharge and equalization, sense amplifiers, write drivers, address decoders, wordline drivers, control logic, clocking, redundancy hooks, and read/write datapaths.\nEvaluate bitcell and peripheral-circuit stability, performance, leakage, dynamic power, and area across process, voltage, temperature, mismatch, and aging conditions.\nOwn transistor-level simulation and signoff using HSPICE, Spectre, FineSim, or comparable tools, including PVT corners, Monte Carlo analysis, parasitic-aware post-layout simulatio and waveform/debug reviews.\nDrive SRAM PPA optimization through circuit sizing, architecture selection, banking and muxing decisions, assist techniques, bias strategies, retention modes, and critical-path analysis.\nDefine timing, power, noise, and functional characterization methodologies and generate validated data for memory models, compiler views, SoC integration, and product signoff.\nPartner with layout engineers on floorplanning, bitcell-array composition, matching, critical-net routing, clock,also control distribution, parasitic reduction, and layout-dependent effects.\nSupport memory-compiler development by defining legal configurations, architecture templates, circuit collateral, generation rules, validation checks, and release-quality views for multiple macro instances.\nDevelop or improve automation for macro assembly, simulation setup, corner execution, results extraction, characterization, validation, and regression using Python, Tcl, Perl, SKILL, or similar languages.\nPlan and support SRAM testchips, including memory-instance selection, PPA objectives, test access, measurement structures, characterization plans. Alignment with process-learning goals.\nLead pre-silicon verification, silicon bring-up, post-silicon characterization, failure debug, and model-to-silicon correlation in partnership with product and silicon-test teams.\nCreate clear circuit specifications, design-review material, verification plans, characterization reports, and release documentation with traceable assumptions and decisions.\nMentor engineers on memory-circuit fundamentals, simulation field, PPA analysis, debug methods, and reusable build practices.\nExplore AI-assisted engineering workflows for specification extraction, circuit and block partitioning, test-mode enrichment, design-flow automation, regression analysis and documentation while maintaining human technical review.\nTechnical Scope\nSRAM and register-file architectures, bit cell arrays, local and global datapaths, sensing, write paths, decoding, control, clocking, test access, and retention behavior.\nLow-power and high-performance design techniques including assist circuits, biasing, leakage reduction, dynamic-power optimization, robust low-voltage operation, and variation-aware sizing.\nMemory compilers and configurable macro generation. This includes architecture templating, legal configuration space, multi-view collateral, validation, and customer or SoC integration support.\nCircuit verification and characterization using SPICE, Verilog-based checks, PVT analysis, Monte Carlo mismatch, extracted post-layout simulation, and timing/power model correlation.\nTestchip development, silicon characterization, debug, shmoo analysis, margin assessment, model calibration and process collaboration.\nMinimum Qualifications\nBS/MS/PhD in Electrical Engineering, Electronics, VLSI, Microelectronics, Computer Engineering, or a related field.\nProven experience in SRAM, register-file, ROM, DRAM peripheral, or other custom-memory circuit design.\nStrong knowledge of CMOS transistor-level circuit design, memory architecture, static and dynamic timing behavior, power analysis, signal integrity, and process variation.\nHands-on experience with Cadence Virtuoso and SPICE-class simulators such as HSPICE, Spectre, or FineSim.\nExperience performing PVT-corner, Monte Carlo, parasitic-aware post-layout, and power/timing characterization analyses.\nAbility to translate product or testchip requirements into circuit architecture, measurable design targets, verification plans, and release criteria.\nExperience collaborating with layout, CAD, process/foundry, verification, product, and chip testing groups.\nClear technical communication and interpersonal skills.\nAbility to operate in a structured manner and problem solving ability.\nThe ability to debug complex circuit or silicon issues using data and waveform evidence.\nPreferred Qualifications\nExperience developing low-power SRAM compilers. Or register-file compilers across multiple technology nodes and foundries.\nExperience with bitcell stability analysis, assist schemes, retention modes, redundancy, test modes, compiler architecture, and generated-memory validation.\nTrack record of taking memory IP from product definition and circuit design through layout, characterization, release, silicon correlation, and customer integration.\nExperience planning memory testchips and partnering with silicon test teams on characterization, debug, and correlation.\nProficiency in Python, along with Tcl, Perl, SKILL, or related programming languages. Will be used for simulation, characterization, regression, and design-flow automation.\nFamiliarity with RTL-to-GDS or digital-on-top methodologies for memory periphery and control logic, alongside full-custom array and critical-circuit design.\nExperience applying agentic AI, coding assistants, or custom LLM agents to specification processing, design automation, validation, or engineering productivity.\nThe US base salary range that Micron Technology estimates it could pay for this full-time position is:\n$153,000.00 - $267,000.00 a yearAdditional compensation may include benefits, bonuses and equity.\nOur salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. \nPlease note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.\nAs a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays.For additional information regarding the Benefit programs available, please see the Benefits Guide posted onmicron.com/careers/benefits.\nMicron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status,disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.\nTo learn about yourright to work click here.\nTo learn more about Micron, please visit micron.com/careers\nUS Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at  or 1-800-336-8918 (select option #3)\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\nAI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.","description_format":"text","description_chars":10320,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity","Parental leave"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Enterprise Storage Systems","Semiconductor Manufacturing","Memory & Storage Chips"],"lifecycle":[{"event":"open","at":"2026-11-07T01:27:07Z"}],"visa":[{"country":"US","licensed_sponsor":true,"adverts_offering_sponsorship_24m":0,"sanctioned_now":false,"evidence":"H-1B filings in 12 months: 535 · green card filings: 199","filings_12m":535,"filings_prev_12m":562,"green_card_filings_12m":199,"median_offered_wage_usd":127078,"route":null,"cap_exempt":false,"checked_at":"2026-11-08T10:45:15+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":216}],"liveness":{"score":99,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.993,"p_room":1,"age_days":2,"expected_fill_days":49,"reasons":["conf:5","urgency","velocity","win:early","comp:brand"],"computed_at":"2026-11-08T05:47:12Z"},"pay":null,"html_url":"https://alion.io/job/micron-technology-sram-design-lead","json_url":"https://alion.io/job/micron-technology-sram-design-lead.json","meta":{"generated_at":"2026-11-08T21:57:51Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":45799,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-09T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":37},"rest":"https://alion.io/mcp/rest/get_company?id=37"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fmicron-technology-sram-design-lead"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fmicron-technology-sram-design-lead"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fmicron-technology-sram-design-lead"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/micron-technology-sram-design-lead\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fmicron-technology-sram-design-lead"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3903115}},{"tool":"search_jobs","arguments":{"company":"micron.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3903115},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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