{"id":1169902,"url":"https://alion.io/job/micron-technology-staff-engineer-asic-ip-sta","title":"Staff Engineer, ASIC IP STA","company":{"id":37,"name":"Micron Technology","domain":"micron.com","url":"https://alion.io/company/micron-technology","size_band":"5000+","is_staffing_agency":false,"is_intermediary":false,"ats_vendor":"Workday","truth_index":{"grade":"B","score":79,"open_postings":767,"ghost_share":0,"stale_share":0.832,"repost_share":0,"time_to_fill_p50_days":25,"computed_at":"2026-09-24T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"hiring_geo_confidence":"explicit","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":50000,"max_usd":101000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":316},"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Tempus","optional":false},{"name":"Python","optional":false},{"name":"AI Agents","optional":true}],"status":"live","first_seen_at":"2026-09-24T06:32:11Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-09-24T09:32:12Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\nASIC IP STA Engineer (6-10 Years) | DDR PHY / ONFI PHY / IO Expander\nLocation: Bengaluru, India\nExperience: 6-10 Years\nEnducational Qualification: BE/B-Tech/M-Tech (EEE, ECE, Micron Electronics, VLSI)\nKey Requirements\nMember of the AMS IP Physical Design team, responsible for post-layout STA signoff and timing closure of high-speed interface IPs, with close collaboration across IP Design, SoC Synthesis, and SoC Physical Design teams throughout IP development and SoC integration.\n6-10 years of experience in Static Timing Analysis (STA) with a proven track record of 4+ successful tapeouts.\nStrong hands-on expertise with Cadence Tempus (preferred).\nIn-depth experience in MMMC timing analysis and closure across functional, scan, MBIST, and other DFT modes.\nExperience working on high-speed Memory Interface IPs such as DDR PHY, ONFI PHY, IO Expander (IOE), or similar high-performance interface designs.\nStrong understanding of timing constraints development, validation, and debug, including clocks, generated clocks, timing exceptions, and mode-specific constraints.\nExperience in Liberty (.lib) and ETM timing model generation, validation, correlation, and quality assessment.\nAbility to deliver early timing models (.lib/ETM) and ensure high-quality timing collateral to enable smooth and predictable SoC integration.\nHands-on experience with SDF generation, validation, and Gate-Level Simulation (GLS) support for verification teams.\nSolid understanding of setup/hold analysis, recovery/removal checks, pulse-width verification, OCV/AOCV/POCV methodologies, and SI-aware timing signoff.\nExperience with the Cadence digital implementation and signoff flow, including Genus, Innovus, and Tempus.\nProficiency in TCL and/or Python for timing analysis, methodology development, and flow automation.\nExposure to AI/ML-enabled EDA methodologies, leveraging AI-assisted workflows for timing analysis, timing closure, constraint validation, root-cause analysis, and productivity improvement.\nStrong analytical, debugging, communication, and stakeholder management skills, with the ability to drive timing closure across cross-functional teams.\nPreferred Qualifications\nExperience with advanced-node, high-frequency designs including LPDDR/DDR, ONFI, IO Expander, or similar memory and interface IPs.\nExposure to AMS/Digital-on-Top IP development flows and timing signoff challenges associated with mixed-signal integrations.\nFamiliarity with AI-powered EDA solutions, Agentic AI workflows for design automation and productivity enhancement.\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich lifefor all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities - from the data center to the intelligent edge and across the client and mobile user experience.\nTo learn more, please visit micron.com/careers\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\nTo request assistance with the application process and/or for reasonable accommodations,please \nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\nAI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.","description_format":"text","description_chars":4773,"description_truncated":false,"requirements":{"experience_years_min":6,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Consumer Electronics","Hardware","Manufacturing","AI Infrastructure"],"lifecycle":[{"event":"open","at":"2026-09-24T06:32:11Z"}],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":25,"reasons":["conf:2","win:early","comp:brand"],"computed_at":"2026-09-24T12:04:59Z"},"pay":null,"html_url":"https://alion.io/job/micron-technology-staff-engineer-asic-ip-sta","json_url":"https://alion.io/job/micron-technology-staff-engineer-asic-ip-sta.json","meta":{"generated_at":"2026-09-24T12:04:59Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers"}}