{"id":1953415,"url":"https://alion.io/job/microsoft-principal-silicon-design-verification-manager","title":"Principal Silicon Design Verification Manager","company":{"id":18,"name":"Microsoft","domain":"microsoft.com","url":"https://alion.io/company/microsoft","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"B","score":75,"open_postings":116,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-15T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Tel Aviv, Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":106000,"max_usd":242000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":696},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Windows","optional":false},{"name":"Cadence Palladium","optional":true},{"name":"Formal Verification","optional":true},{"name":"Git","optional":true},{"name":"Linux","optional":true},{"name":"Python","optional":true},{"name":"SystemVerilog","optional":true},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2026-08-03T14:56:30Z","employer_posted_date":"2026-10-06","last_verified_at":"2026-10-15T07:39:06Z","board_verified":true,"closed_at":null,"days_open":72,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":72},"description":"OverviewThe WSSI (Windows Silicon System Integration) team is looking for an experienced Silicon Design Verification Team Lead to lead verification for complex silicon subsystems that are part of advanced solutions delivered in Windows client products.\nThis is an opportunity for an excellent DV leader to combine people leadership with meaningful hands-on technical contribution. You will lead a silicon engineering team that includes design verification, silicon design, and physical design engineers, while serving as the technical anchor for the team's verification strategy, execution, and quality.\nThe team works on complex security-oriented silicon subsystems that require rigorous pre-silicon verification and close collaboration with architecture, design, firmware, system engineering, and physical design partners to deliver robust silicon quality.\nWe are looking for a leader who is passionate about building excellent teams, driving rigorous execution, contributing hands-on to complex verification challenges, and continuously improving verification methodologies - including applying modern AI-assisted techniques to improve productivity, debug efficiency, and verification quality.\nResponsibilities\nLead, grow, and mentor a silicon engineering team that includes design verification, silicon design, and physical design engineers, while fostering a culture of technical excellence, ownership, collaboration, and continuous learning.\nOwn and drive the verification strategy for complex silicon subsystems from planning through execution, closure, and emulation readiness.\nProvide substantial hands-on technical contribution and leadership in verification planning, testbench architecture, debug, coverage analysis, regression quality, and verification closure.\nBuild and promote modern verification workflows, including AI-assisted techniques that improve verification environment development, automation, debug efficiency, coverage analysis, and execution quality.\nDefine verification plans, quality metrics, regression strategy, coverage goals, and emulation readiness plans aligned with project milestones.\nCollaborate closely with architecture, design, system engineering, firmware, and physical design partners to identify risks early, resolve complex issues, and deliver high-quality silicon subsystems.\nQualifications\nB.Sc., M.Sc., or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field.\nProven experience and technical excellence in pre-silicon design verification for complex IPs, subsystems, or SoCs, including subsystem integration, and third-party IP integration.\nSignificant hands-on experience with modern DV methodologies, verification planning, testbench development, regressions, coverage analysis, debug, and verification closure.\nExperience as a people manager or technical leader driving verification work across multiple engineers.\nPreferred Qualifications -\nProficiency in SystemVerilog-based verification environments and methodologies such as UVM, assertions, constrained-random verification, and coverage-driven verification, along with Python-based automation and modern verification infrastructure workflows.\nExperience applying AI-assisted techniques to improve silicon design or verification productivity, debug, coverage, automation, or workflow efficiency.\nHands-on experience with Python, Linux, Git-based development workflows, and automation infrastructure.\nExperience with formal verification, low-power verification, performance verification, or subsystem-level verification.\nExperience with security-oriented silicon subsystems, including crypto engines, memory protection, secure boot, trusted execution, or related hardware security domains.\nExperience with emulation platforms such as Palladium.\nExperience leading or working in teams that include both design and verification engineers.\nFamiliarity with physical design considerations, synthesis, constraints, timing closure, or design handoff flows.\nProven problem-solving, communication, ownership, and cross-team collaboration skills. \n#W+D\n#WSSIIL\n#WSSI\n#IL\nThis position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.\nMicrosoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. 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