{"id":2746537,"url":"https://alion.io/job/microsoft-senior-logic-design-engineer-2","title":"Senior Logic Design Engineer","company":{"id":18,"name":"Microsoft","domain":"microsoft.com","url":"https://alion.io/company/microsoft","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"B","score":75,"open_postings":93,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":28,"computed_at":"2026-10-16T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hillsboro, United States","Washington, United States","Mountain View, United States","Austin, United States","Raleigh, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":119800,"max":234700,"currency":"USD","period":"year","gross":null,"usd_annual":234700},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Azure","optional":false},{"name":"OneDrive","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-10-13T03:58:51Z","employer_posted_date":"2026-10-16","last_verified_at":"2026-10-17T02:14:05Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"OverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.\nThe Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more.\nAs Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Silicon Logic Design team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for experienced engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.\nWe are looking for a Senior Logic Design Engineer to join the team driving high-quality RTL towards Physical Design handoff with a particular emphasis on static timing analysis, SDC constraints, and synthesis correlation and quality.\n#SCHIE #CSME\nResponsibilities\nThe candidate for this position will be expected and able to complete the following responsibilities:\nDesign, develop, and maintain robust timing (SDC) constraints ensuring functional correctness, hierarchical consistency, and tool compatibility while enabling PPA targets.\nLeverage state of the art tools to generate constraints and perform quality assurance for PD and STA consumption.\nCollaborate and support Physical Design, STA, and DFT teams with collaterals from initial RTL handoff to tape out.\nAnalyze and debug synthesis results to drive RTL optimization towards achieving PPA targets\nAutomate tasks using scripting for efficiency\nUtilize AI for gaining efficiency within process and development\nContinue to grow your micro-architectural knowledge and contribute to unit, sub-system and SOC micro-architecture\nDevelopment and integration of various functional block RTL\nPerform design quality checks such as Timing closure, Lint, CDC, Synthesis, Low Power Intent\nExercise the functionality of the block by writing basic tests and debug for various features at IP and SoC levels as deemed necessary. \nDelight your customers by providing high-quality functional blocks on schedule and with professional integrity\nChallenge the status quo with growth mindset.\nMentor team members and summer interns for a growing team\nQualifications\nRequired Qualifications:\nDoctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience\nOR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience\nOR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience\nOR equivalent experience.\n\nOther Requirements\nAbility to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. \nThis role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.\nPreferred Qualifications:\nExperience in static timing analysis and logic domain including SDC/Timing Constraint generation, analysis, and quality assurance.\nExperience with synthesis script setup, debug, analysis, and drive to quality targets.\nKnowledge of logic design flow including Low Power Analysis, UPF, RTL coding, Synthesis, timing constraints, timing closure.\nDemonstrated expertise in Computer Architecture, Digital Design, IP/SoC design principles as part of SoC and/or IP development.\nHighly Proficient in Verilog/System Verilog coding constructs.\nKnowledge of front-end tools (VCLP, Verilog simulators, Connectivity tools, low power static checkers, linting)\nDemonstrated experience and knowledge of clock crossings, and power/UPF in design\nAbility to write scripts using Perl, Tcl, Python etc.\nFamiliarity with Industry standard interface protocols (ARM) is a plus.\nFamiliarity with Formal Equivalence Verification and Power Analysis is a plus.\nVerbal and written communication skills.\n\nSilicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.\nCertain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:\nhttps://careers.microsoft.com/us/en/us-corporate-pay\nThis position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.\nMicrosoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.","description_format":"text","description_chars":7510,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Console Games","Cloud Platforms (IaaS & PaaS)","Gaming Consoles","Developer Tools"],"lifecycle":[{"event":"open","at":"2026-10-16T22:23:12Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":4,"expected_fill_days":28,"reasons":["conf:3","win:early","comp:brand"],"computed_at":"2026-10-17T05:21:26Z"},"pay":{"stated_usd_annual":234700,"is_top_pay":true},"html_url":"https://alion.io/job/microsoft-senior-logic-design-engineer-2","json_url":"https://alion.io/job/microsoft-senior-logic-design-engineer-2.json","meta":{"generated_at":"2026-10-17T05:21:26Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":7206,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-18T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":18},"rest":"https://alion.io/mcp/rest/get_company?id=18"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fmicrosoft-senior-logic-design-engineer-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fmicrosoft-senior-logic-design-engineer-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fmicrosoft-senior-logic-design-engineer-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/microsoft-senior-logic-design-engineer-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fmicrosoft-senior-logic-design-engineer-2"}]}