{"id":1831593,"url":"https://alion.io/job/microsoft-senior-serdes-analog-layout-design-engineer","title":"Senior SerDes & Analog Layout Design Engineer","company":{"id":18,"name":"Microsoft","domain":"microsoft.com","url":"https://alion.io/company/microsoft","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"B","score":75,"open_postings":106,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-14T06:34:16Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Raleigh, United States","Austin, United States","Columbia, United States","Washington, United States","Boise, United States","Hillsboro, United States","Mountain View, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":119800,"max":234700,"currency":"USD","period":"year","gross":null,"usd_annual":234700},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Azure","optional":false},{"name":"Path Planning","optional":false},{"name":"Python","optional":false},{"name":"Ansys Totem","optional":true},{"name":"Cadence Virtuoso","optional":true},{"name":"Cadence Voltus","optional":true},{"name":"Siemens Calibre","optional":true}],"status":"live","first_seen_at":"2026-09-04T22:05:55Z","employer_posted_date":"2026-10-01","last_verified_at":"2026-10-14T12:57:27Z","board_verified":true,"closed_at":null,"days_open":39,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":39},"description":"OverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s Intelligent Cloud mission. SCHIE delivers core infrastructure and foundational technologies supporting Azure, Microsoft 365, Teams, Xbox, and next-generation AI platforms at hyperscale, with a focus on high-quality, efficient, and trusted cloud hardware solutions.\nAs Microsoft’s cloud and AI businesses continue to grow, high-speed die-to-die (D2D) connectivity is critical to delivering scalable, power-efficient custom silicon. The Semi & Custom IP team develops advanced analog and mixed-signal IP, including D2D SerDes interfaces, for next-generation AI accelerators, cloud infrastructure, and custom silicon platforms powering Microsoft’s future AI services and datacenter offerings.\nWe are looking for a Senior D2D SerDes & Analog Layout Design Engineer to be a hands-on technical contributor and layout lead for matching-critical analog and D2D SerDes physical implementation. This high-visibility role will own complex subsystem deliverables, guide layout execution and technical reviews, collaborate across design and integration teams, and drive production-ready IP from planning through tapeout. The position offers opportunities to broaden technical scope, deepen D2D and advanced-node expertise, and grow technical leadership through direct work on strategic silicon programs.\nResponsibilities\nDrive physical implementation of complex D2D SerDes and analog/mixed-signal IP in advanced process technologies, from floorplanning through tapeout, signoff, and integration.\nOwn or co-own top-level D2D analog front-end floorplanning and integration, including partitioning, hierarchy, die-edge constraints, bump or micro-bump alignment, ESD interfaces, power distribution, sensitive routing, and package-aware implementation tradeoffs.\nEstablish matching and parasitic-control strategies for critical circuits using symmetry, common-centroid placement, interdigitation, device orientation control, dummy structures, shielding, guard rings, isolation, return-path planning, and gradient mitigation.\nHelp lead D2D layout execution across multiple blocks and contributors by defining implementation plans, coordinating technical work, reviewing layouts, resolving cross-block dependencies, and supporting milestone closure.\nPartner with circuit design leadership to translate electrical requirements into physical implementation constraints and make layout-versus-circuit tradeoffs that improve system-level power, performance, area, signal integrity, reliability, and yield.\nIdentify and resolve layout risks for high-speed transmitter, receiver, clocking, bias, equalization, PLL/DLL, and related analog front-end circuitry.\nCollaborate across signal integrity, package, ESD, physical design, CAD, foundry, reliability, and SoC teams to align interface definitions and integration requirements for the assigned subsystem.\nOwn physical verification and signoff closure, including DRC, LVS, ERC, antenna, density, extraction review, EMIR, reliability analysis, layout-dependent effects, and complex cross-hierarchy debug.\nContribute to layout quality criteria, review checklists, release requirements, and signoff evidence for internally and externally developed D2D and analog IP.\nDeliver production-ready IP collateral, including GDS/OASIS, LEF abstracts, integration views, interface documentation, waiver rationale, review records, and signoff packages for SoC and package integration.\nDevelop and improve analog layout methodologies, reusable templates, automation flows, and productivity solutions using SKILL, TCL, Python, or similar scripting languages.\nProvide technical guidance and mentorship through design reviews, coaching, documentation, and sharing of advanced-node analog and D2D layout practices.\nCoordinate technical execution with contractors, vendors, and geographically distributed design partners by setting expectations, reviewing quality, resolving issues, and supporting program commitments.\nCommunicate technical status, risks, tradeoffs, and recommendations to engineering and program stakeholders for assigned D2D deliverable\nQualifications\nRequired Qualifications:\nDoctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.\nOther:\nAbility to meet Microsoft, customer, and/or government security screening requirements is required for this role. These requirements include, but are not limited to, the following specialized security screening: Microsoft Cloud Background Check. This position is required to pass the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.\nThis role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.\nPreferred Qualifications:\n5+ years of analog or mixed-signal layout experience, including matching-critical transistor-level layout in advanced process technologies.\nExperience owning significant analog or mixed-signal layout deliverables through physical verification, signoff, and tapeout.\nExperience using Cadence Virtuoso and Siemens/Mentor Calibre physical verification tools.\nExperience with DRC, LVS, ERC, antenna, extraction-aware layout, and advanced-node physical signoff.\nExperience collaborating across circuit design and physical implementation teams and providing technical guidance or design reviews to other layout contributors.\nExperience with high-speed SerDes, D2D interfaces, or comparable high-performance analog/mixed-signal IP, including transmitter, receiver, clocking, bias, equalization, PLL/DLL, or related circuitry.\nDeep understanding of analog matching, symmetry, layout-dependent effects, device orientation, process gradients, coupling, isolation, shielding, return paths, and parasitic optimization.\nFamiliarity with D2D standards or implementations such as UCIe, BoW, or proprietary die-to-die links.\nExperience with advanced packaging and chiplet integration, including die-edge planning, bump or micro-bump interfaces, ESD structures, package escape, power delivery, and signal-integrity constraints.\nExperience influencing floorplan, interface, or circuit decisions based on physical implementation feasibility and extracted-layout results.\nExperience leading top-level assembly and verification of analog subsystems containing blocks developed by multiple engineers or external partners.\nExperience with EMIR and reliability signoff using Ansys Totem, Cadence Voltus, or equivalent tools.\nExperience with Cadence automated place-and-route (APR) flows, including floorplanning, placement, clock or signal routing, physical optimization, and integration of custom analog or mixed-signal IP with digitally implemented logic.\nExperience with FinFET and/or Gate-All-Around technologies and advanced nodes such as 5nm, 3nm, or beyond.\nDemonstrated ability to mentor engineers, lead technical reviews, and resolve complex layout issues across team boundaries.\nExperience managing technical execution with geographically distributed teams, contractors, vendors, or design-service partners across multiple milestones or programs.\nSilicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.\nCertain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:\nhttps://careers.microsoft.com/us/en/us-corporate-pay\nThis position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.\nMicrosoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.","description_format":"text","description_chars":9744,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Console Games","Cloud Platforms (IaaS & PaaS)","Gaming Consoles","Developer Tools"],"lifecycle":[{"event":"open","at":"2026-10-04T12:19:11Z"}],"visa":[],"liveness":{"score":21,"band":"cold","label":"Long shot","p_open":1,"p_active":0.46,"p_room":0.45,"age_days":39,"expected_fill_days":22,"reasons":["conf:2","stale_co","velocity","win:tail","comp:brand"],"computed_at":"2026-10-14T06:34:16Z"},"pay":{"stated_usd_annual":234700,"is_top_pay":true},"html_url":"https://alion.io/job/microsoft-senior-serdes-analog-layout-design-engineer","json_url":"https://alion.io/job/microsoft-senior-serdes-analog-layout-design-engineer.json","meta":{"generated_at":"2026-10-14T14:30:34Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":17887,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-15T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":18},"rest":"https://alion.io/mcp/rest/get_company?id=18"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fmicrosoft-senior-serdes-analog-layout-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fmicrosoft-senior-serdes-analog-layout-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fmicrosoft-senior-serdes-analog-layout-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/microsoft-senior-serdes-analog-layout-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fmicrosoft-senior-serdes-analog-layout-design-engineer"}]}