{"id":1266529,"url":"https://alion.io/job/mirafra-technologies-seniorlead-dft-engineer","title":"Senior/Lead DFT Engineer","company":{"id":3833,"name":"Mirafra Technologies","domain":"mirafra.com","url":"https://alion.io/company/mirafra-technologies","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":14,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys TestMAX","optional":false},{"name":"Tessent","optional":false}],"status":"live","first_seen_at":"2026-09-04T05:05:53Z","employer_posted_date":null,"last_verified_at":"2026-09-04T05:05:53Z","board_verified":false,"closed_at":null,"days_open":28,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":28},"description":"Job Overview : \n\nWe are looking for experienced DFT Engineers to join our VLSI team. The role involves DFT architecture, implementation, verification, and silicon bring-up/debug across various levels of experience.\n\nKey Responsibilities : \n\n- Develop and implement Design-for-Test (DFT) architecture and methodologies for complex SoCs.\n\n- Work on Scan insertion, ATPG, MBIST, LBIST, JTAG/Boundary Scan, and test compression.\n\n- Perform DFT RTL integration, synthesis, and implementation.\n\n- Develop and debug ATPG patterns, analyze coverage, and resolve test-related issues.\n\n- Work on scan chain analysis, test modes, constraints, and DFT timing.\n\n- Perform DFT verification including simulations, ATPG validation, and coverage analysis.\n\n- Debug DFT-related issues across RTL, gate-level, and physical implementation stages.\n\n- Collaborate with RTL, STA, Physical Design, Verification, and Silicon teams.\n\n- Support DFT signoff, production test requirements, and silicon bring-up/debug.\n\n- Develop scripts and automation using TCL, Python, Perl, or Shell where applicable.\n\n- For senior/lead roles, drive DFT methodology, architecture, technical reviews, and project execution.\n\nRequired Skills : \n\n- Strong understanding of DFT concepts and methodologies.\n\n- Hands-on experience with Scan, ATPG, MBIST, LBIST, JTAG, Boundary Scan, and Compression.\n\n- Experience with industry-standard DFT tools such as Synopsys TestMAX/TetraMAX, Cadence Modus, Mentor Tessent, or equivalent.\n\n- Good understanding of STA, synthesis, RTL, and physical design flows.\n\n- Experience with DFT constraints, test clocks, test modes, scan chains, and coverage analysis.\n\n- Good scripting/programming skills in TCL, Python, Perl, or Shell.\n\n- Strong debugging, problem-solving, and communication skills.\n\nExperience Levels : \n\n- 3 - 6 Years : DFT implementation, scan insertion, ATPG, pattern generation, coverage analysis, and debugging.\n\n- 6 - 10 Years : End-to-end DFT implementation, complex SoC DFT, methodology development, and technical ownership.\n\n- 10 - 14 Years : DFT architecture, project ownership, advanced ATPG/MBIST/JTAG, signoff, and cross-functional leadership.\n\n- 14 - 17 Years : DFT technical leadership/architecture, methodology definition, customer interaction, and mentoring of DFT teams.\n\nEducation : \n\n- B. Tech/M. Tech in Electronics, Electrical Engineering, VLSI, or a related field.\n\nPreferred : \nSkills\nDFT, VLSI, MBIST, RTL, RTL Design, Physical Design, Verification, TCL, Python","description_format":"text","description_chars":2486,"description_truncated":false,"requirements":{"experience_years_min":14,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-25T22:00:00Z"}],"liveness":{"score":21,"band":"cold","label":"Long shot","p_open":0.85,"p_active":0.549,"p_room":0.45,"age_days":28,"expected_fill_days":15,"reasons":["seen:28","win:tail"],"computed_at":"2026-10-02T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/mirafra-technologies-seniorlead-dft-engineer","json_url":"https://alion.io/job/mirafra-technologies-seniorlead-dft-engineer.json","meta":{"generated_at":"2026-10-03T01:13:54Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":1124,"day_limit":5000,"remaining_today":3876,"minute_limit":60,"resets_at":"2026-10-04T00:00:00Z"}}}