{"id":1292876,"url":"https://alion.io/job/mirafra-technologies-soc-emulation-engineer","title":"SoC Emulation Engineer","company":{"id":3833,"name":"Mirafra Technologies","domain":"mirafra.com","url":"https://alion.io/company/mirafra-technologies","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India","Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":16500,"max_usd":41000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":13},"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"OpenGL","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys ZeBu","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"C++","optional":true},{"name":"Cadence Palladium","optional":true},{"name":"Linux","optional":true},{"name":"Siemens Veloce","optional":true}],"status":"live","first_seen_at":"2026-08-11T06:06:10Z","employer_posted_date":null,"last_verified_at":"2026-08-11T06:06:10Z","board_verified":false,"closed_at":null,"days_open":49,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":49},"description":"Key Responsibilities : \n\n- Build, compile, and deploy GPU SoC emulation models on Synopsys ZeBu platforms.\n\n- Perform design partitioning and mapping for large GPU subsystems, including shader cores, compute units, memory controllers, and interconnects.\n\n- Optimize emulation models for high-bandwidth and concurrency-intensive workloads.\n\n- Debug issues across RTL, compilation, elaboration, and runtime phases.\n\n- Perform initial debug triage and root-cause analysis of test failures.\n\n- Support GPU software bring-up, including firmware, drivers, and kernel integration.\n\n- Enable and debug graphics and compute workloads such as OpenGL and Vulkan.\n\n- Collaborate with Architecture, RTL, Design Verification, and Software teams.\n\n- Drive emulation performance tuning, stability, and turnaround-time improvements.\n\n- Develop automation for build, regression, and emulation workflows.\n\nRequired Skills & Experience : \n\n- Bachelor's/Master's degree in Electronics, Electrical, Computer Engineering, or related field.\n\n- 6-9 years of experience in SoC emulation, verification, or related semiconductor domains.\n\n- Strong hands-on experience with Synopsys ZeBu and ZeBu build flows.\n\n- Strong knowledge of Verilog/SystemVerilog.\n\n- Understanding of GPU architecture, including parallel pipelines, scheduling, caches, memory controllers, and memory bandwidth.\n\n- Experience with emulation model build, compilation, debug, and synthesis constraints.\n\n- Strong debugging and problem-solving skills.\n\n- Experience with scripting using Python, Tcl, Shell, or Perl.\n\nPreferred Skills : \n\n- Experience with GPU graphics pipelines or AI accelerators.\n\n- Exposure to Cadence Palladium or Siemens Veloce.\n\n- Knowledge of Vulkan/OpenGL.\n\n- Linux, firmware, or driver bring-up experience.\n\n- Understanding of memory subsystem debugging and performance bottlenecks.\n\n- Experience automating build and regression flows.\n\nKey Deliverables : \n\n- Stable and high-performance GPU emulation models.\n\n- Reduced compile and runtime turnaround time.\n\n- Efficient debugging and triaging of GPU workloads and test failures.\n\n- Automated and scalable emulation build and regression workflows.\nSkills\nSoC, Verilog, System Verilog, Python, GPU, Emulation, Zebu, RTL, Design Verification","description_format":"text","description_chars":2257,"description_truncated":false,"requirements":{"experience_years_min":6,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T08:01:01Z"}],"liveness":{"score":7,"band":"cold","label":"Long shot","p_open":0.4,"p_active":0.399,"p_room":0.45,"age_days":48,"expected_fill_days":30,"reasons":["seen:48","win:tail"],"computed_at":"2026-09-29T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/mirafra-technologies-soc-emulation-engineer","json_url":"https://alion.io/job/mirafra-technologies-soc-emulation-engineer.json","meta":{"generated_at":"2026-09-30T03:13:45Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":2388,"day_limit":5000,"remaining_today":2612,"minute_limit":60,"resets_at":"2026-10-01T00:00:00Z"}}}