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Salary
≈ $79k – $230k per year (Estimated)
Location
In office (Haifa)
Seniority
Senior · 5+ years exp
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 12, 2026. First seen by Alion on Jun 21, 2026. Mobileye scores B on the Alion truth index.

Overview
Company
Impact
Profile match
Mobileye is an Israeli company founded in Jerusalem in 1999 by the computer scientist Amnon Shashua and the entrepreneur Ziv Aviram, built on the then-contrarian idea that a single camera and clever software could handle driver assistance without radar or lidar. Its EyeQ system-on-chip has shipped in more than two hundred million vehicles, making it the dominant supplier of vision-based driver assistance to the global car industry. Acquired by Intel for fifteen billion dollars in 2017 and returned to public markets in 2022, the company now sells escalating tiers from basic assistance through the SuperVision and Chauffeur hands-off systems up to the fully driverless Mobileye Drive platform.

Are you looking to take an active part in shaping next-generation EyeQ SoC technology, driving the process all the way from initial definition to Tape-Out?

Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to execution and full signoff. You will work closely with Design and Architecture teams on RTL modifications and design reviews to ensure seamless convergence.

We’re expanding our teams and looking for an Experienced Physical Design Engineer who is ready to make a massive impact

NOTE: By applying for this position, you will have the opportunity to indicate your preferred work location: Haifa or Petach Tikva.

What will your job look like:

  • Hands-on physical design block owner, leading the process from RTL to GDS .
  • Lead floorplan exploration in collaboration with Front-End and Architecture teams.
  • STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
  • Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
  • Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).

All you need is:

  • BSc or MSc in Computer Engineering or Electrical Engineering.
  • 5+ years of experience in the Physical Design field.
  • Proficiency in scripting languages (Tcl, Python, Perl, or tcsh).
  • A team player with excellent communication skills and a “can-do” attitude.

Nice to have:

  • Experience in developing or maintaining implementation tools and design flows.
  • Experience with high-speed interfaces (DDR/PCIE).
  • Experience with advanced nodes (5nm and below).
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