{"id":2301044,"url":"https://alion.io/job/mobileye-senior-verification-engineer","title":"Senior Verification Engineer","company":{"id":174,"name":"Mobileye","domain":"mobileye.com","url":"https://alion.io/company/mobileye","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"A","score":92,"open_postings":52,"ghost_share":0,"stale_share":0.308,"repost_share":0,"time_to_fill_p50_days":59,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ramat Gan, Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":94000,"max_usd":214000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1655},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-08-23T07:55:43Z","employer_posted_date":"2026-08-23","last_verified_at":"2026-10-17T11:07:19Z","board_verified":true,"closed_at":null,"days_open":55,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":55},"description":"Mobileye’s Unit Level Verification Team in Haifa is looking for an experienced verification engineer to be involved in the development of Mobileye’s future AI and deep learning HW accelerators.\nThis is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver Mobileye’s EyeQ future chips, aimed to power the world’s first fully Autonomous Vehicle!\nWhat will your job look like:\nDefine, implement and enhance verification environments using UVM methodology.\nWrite and debug tests that combine UVM methodology and SW code.\nIdentify and write various types of coverage measures.\nCollaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.\nIntegrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs. \nAll you need is:\nBSc in electrical engineering, computer engineering, or computer science.\n8+ years of experience working in verification environment, tests, and test bench development (SV/UVM/C/C++).\nSystem Verilog writing skills, preferably in OVM/UVM.\nSW embedded experience, C/C++ skills.\nTestPlan defining and Coverage-Driven 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