{"id":1272906,"url":"https://alion.io/job/modernize-chip-solutions-rtl-integration-engineer","title":"RTL Integration Engineer","company":{"id":8259,"name":"Modernize Chip Solutions","domain":"modernchipsolutions.com","url":"https://alion.io/company/modernize-chip-solutions","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":4500000,"max":6000000,"currency":"INR","period":"year","gross":null,"usd_annual":63108},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Allegro","optional":false},{"name":"Synopsys SpyGlass","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-08-31T06:12:38Z","employer_posted_date":null,"last_verified_at":"2026-08-31T06:12:38Z","board_verified":false,"closed_at":null,"days_open":47,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":47},"description":"Department: Front End Engineering\nReports To: BU Head\nLocation: Bengaluru\nEmployment Type: Full Time\n\nJob Summary\nThe RTL Integration Engineer will be responsible for the integration of third-party ASA IP into the Camera\nSerializer digital subsystem. The role requires strong expertise in RTL integration, digital design, clock-domain\ncrossing, interface adaptation, register and CSR methodology, and integration of digital and Analog/Mixed-Signal\nIP blocks.\nThe engineer will work closely with Design, Architecture, PHY, Verification, and Analog/Mixed-Signal teams to\nensure that integrated IPs meet functional, timing, connectivity, quality, and safety requirements. The role will\ninvolve ownership of IP integration activities from specification understanding through RTL implementation,\nanalysis, lint/CDC closure, subsystem integration, and final sign-off.\n\nKey Skills & Responsibilities\n- Authoring and owning 3rd party IP integration\nOwn the end-to-end integration of third-party IPs into the target digital subsystem. This includes understanding IP\nspecifications and interfaces, defining integration requirements, establishing connectivity between IP blocks,\nresolving interface dependencies, and ensuring that the integrated IP functions correctly within the overall\nsubsystem architecture. The candidate should be comfortable taking ownership of integration issues and working\nwith IP vendors, architects, designers, and verification teams to resolve technical dependencies and integration\nchallenges.\n- ASA-ML-T-22ULL PHY integration\nHands-on experience with ASA-ML-T-22ULL PHY integration is required. The candidate should be able to\nunderstand the PHY interface and associated specifications and successfully integrate the PHY with the\nsurrounding digital logic. Responsibilities include managing digital-side connectivity, interface requirements,\nconfiguration and control paths, and ensuring correct interaction between the PHY and the Camera Serializer\ndigital subsystem.\n- Multi-domain CDC analysis\nPerform Clock Domain Crossing (CDC) analysis across multiple clock domains within the subsystem. The\ncandidate should understand asynchronous clock-domain interactions, identify potential CDC violations, and work\non appropriate synchronization and data-transfer mechanisms. The role involves analyzing CDC reports,\ndebugging violations, coordinating with RTL/design teams, and driving CDC closure while maintaining functional\ncorrectness and reliability of the integrated design.\n- ASEP 8-port interface: 32-to-16-bit width adaptation, async FIFO design, STYPE\nrouting, SOP/EOP framing\nWork on the ASEP 8-port interface, including 32-to-16-bit width adaptation, asynchronous FIFO design, STYPE\nrouting, and SOP/EOP framing. The candidate should be capable of designing and integrating the required RTL\nlogic for data-width conversion and asynchronous data movement while ensuring correct packet/frame handling.\nThe engineer will ensure that Start-of-Packet (SOP) and End-of-Packet (EOP) information is preserved correctly\nand STYPE-based routing operates according to the relevant specification.\n- APB/SOC slave bus bridge; register map ownership; RGGEN-based CSR\nmethodology\nOwn the design and integration of the APB/SoC slave bus bridge, including responsibility for the associated\nregister map. The candidate should have experience defining and implementing register interfaces, understanding\naddress maps, handling read/write transactions, and ensuring correct connectivity between the SoC bus and\nintegrated IP. Experience with RGGEN-based CSR methodology is required, including structured approaches for\ngenerating and managing Control and Status Registers (CSRs).\n- SystemVerilog (RTL and assertions), lint, linting closure, Cadence CDC tool\nStrong hands-on experience with SystemVerilog for RTL development and assertions. The candidate should\nbe capable of writing clean, synthesizable RTL and using assertions to capture design intent and verify key\nfunctional properties. Experience with Cadence HAL/SpyGlass linting, linting closure, and Cadence CDC tools is\nrequired. The candidate should be comfortable analyzing reports, implementing fixes, and driving closure.\n- Working knowledge of ASA-ML DLL, PCS, OAM, PTB, and ASEP layers; PHY\ndatasheet/spec fluency\nWorking knowledge of the ASA-ML DLL, PCS, OAM, PTB, and ASEP layers is expected. The candidate should\nbe comfortable reading and interpreting PHY datasheets and specifications, understanding interface behavior, and\ntranslating protocol and PHY requirements into practical RTL integration activities.\n- Co-simulations between Digital and Analog/Mixed-Signal IP blocks\nExperience with co-simulation between Digital and Analog/Mixed-Signal IP blocks. The candidate should\nunderstand the challenges involved in integrating digital logic with AMS components and participate in\nco-simulation activities to validate interactions between digital and analog/mixed-signal portions of the design.\n- MBIST/LBIST and redundancy\nExperience or working knowledge of MBIST, LBIST, and redundancy mechanisms as part of the overall chip\nintegration and test strategy. The candidate should understand how memory and logic test mechanisms are\nincorporated into the SoC and how these mechanisms interact with the overall digital architecture.\n- Safety mechanism to make whole chip compliant to FuSa requirements\nWork on the integration and implementation of safety mechanisms required to make the whole chip compliant\nwith Functional Safety (FuSa) requirements. The candidate should understand how safety requirements\ntranslate into hardware design and integration requirements and collaborate with architecture, design, verification,\nand safety teams to ensure required mechanisms are correctly implemented and integrated.\n\nQualification & Experience\n- B.E / B.Tech / M.E / M.Tech\n- 8 to 12 Years\nSalary Range: 45 LPA to 60 LPA\nBenefits: As per company policy\nTravel Requirements: As per client requirement\nSkills\nRTL, Mixed Signal, Analog Mixed Signal, IP Integration, System Verilog, Cadence Allegro","description_format":"text","description_chars":6068,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T00:07:01Z"}],"visa":[],"liveness":{"score":9,"band":"cold","label":"Long shot","p_open":0.4,"p_active":0.526,"p_room":0.45,"age_days":46,"expected_fill_days":26,"reasons":["seen:46","win:tail"],"computed_at":"2026-10-17T05:46:00Z"},"pay":{"stated_usd_annual":63108,"is_top_pay":false},"html_url":"https://alion.io/job/modernize-chip-solutions-rtl-integration-engineer","json_url":"https://alion.io/job/modernize-chip-solutions-rtl-integration-engineer.json","meta":{"generated_at":"2026-10-18T00:57:54Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":1607,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-19T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":8259},"rest":"https://alion.io/mcp/rest/get_company?id=8259"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fmodernize-chip-solutions-rtl-integration-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fmodernize-chip-solutions-rtl-integration-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fmodernize-chip-solutions-rtl-integration-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/modernize-chip-solutions-rtl-integration-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fmodernize-chip-solutions-rtl-integration-engineer"}]}