{"id":1276347,"url":"https://alion.io/job/moschip-lead-engineer-physical-design","title":"Lead Engineer - Physical Design","company":{"id":2398746,"name":"MosChip","domain":"moschip.com","url":"https://alion.io/company/moschip","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Keka","truth_index":{"grade":"D","score":53,"open_postings":32,"ghost_share":0.781,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-09-29T05:45:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Synopsys PrimeTime","optional":true}],"status":"live","first_seen_at":"2026-06-19T06:47:52Z","employer_posted_date":"2026-06-19","last_verified_at":"2026-09-28T11:31:48Z","board_verified":true,"closed_at":null,"days_open":102,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":101},"description":"Company Description:\nMosChip® Technologies is a publicly traded company with expertise in SILICON | PRODUCT | AI/ML Engineering solutions. The company has 1250+ engineers located in Silicon Valley-USA and India. MosChip® offers end-to-end silicon design, verification, systems, software, and device engineering solutions, including AI/ML solution design and test automation.\nRole Description:\nThis is a full-time on-site role for a Senior Lead Physical Design Engineer based in Hyderabad. The Senior Physical Design Engineer will be responsible for tasks related to physical design, physical verification, logic design, circuit design, and RTL design in the development of silicon products.\nQualifications:\nHe/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.\nMinimum of 7-15 years of experience in physical design.\nHe/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.\nProvide technical guidance, mentoring to physical design engineers.\nLead a team of Physical design engineers and be responsible for their blocks’ closure\nInterface with front-end ASIC teams to resolve issues.\nLow Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.\nExpertise in Timing closure on high speed interfaces is a plus\nExcellent communication skills.\nStrong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.\nExtensive experience and detailed knowledge in Cadence or Synopsys.\nExpertise in scripting languages such as PERL, TCL.\nStrong Physical Verification skill set.\nStatic Timing Analysis in Primetime or Primetime-SI.\nGood written and oral communication skills. Ability to clearly document plans.\nAbility to interface with different teams and prioritize work based on project needs.","description_format":"text","description_chars":2134,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"},{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Artificial Intelligence","Design & Creative","Science & Engineering"],"lifecycle":[{"event":"open","at":"2026-09-26T01:47:19Z"}],"liveness":{"score":7,"band":"cold","label":"Long shot","p_open":1,"p_active":0.267,"p_room":0.28,"age_days":101,"expected_fill_days":35,"reasons":["conf:18","stale_co","ghost","win:tail","crowd:"],"computed_at":"2026-09-29T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/moschip-lead-engineer-physical-design","json_url":"https://alion.io/job/moschip-lead-engineer-physical-design.json","meta":{"generated_at":"2026-09-30T00:41:44Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":549,"day_limit":5000,"remaining_today":4451,"minute_limit":60,"resets_at":"2026-10-01T00:00:00Z"}}}